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CAREER: Addressing Deepening Variability Challenges for Next-Generation Margin-Free VLSI Computing Platform Design

CAREER: Addressing Deepening Variability Challenges for Next-Generation Margin-Free VLSI Computing Platform Design
职业生涯:解决下一代无裕度 VLSI 计算平台设计日益深化的可变性挑战
批准号:
1453142
负责人:
Mingoo Seok
金额:
$46.1万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-03-01 至 2021-02-28

项目摘要

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中文摘要
翻译
这个职业项目的目标是解决当今计算芯片设计中不断加深的变异性挑战。在过去的40年里,半导体技术突飞猛进,使计算芯片成为我们信息时代的主要主力。进一步改进的努力仍在继续,但科学家和工程师最近观察到,研究努力的回报正在减少。造成这种情况的主要原因之一是芯片内部、芯片之间以及芯片生命周期内电路性能的不断变化。虽然传统的设计实践忽略了性能改进的可变性方面,但这一方面现在已经变得过于引人注目,简单地放弃它是令人望而却步的。该项目将从根本上解决这个问题。该项目还包括在当前框架内针对初中生、本科生和研究生以及在职专业人员的教育/推广计划。更具体地说,该项目将寻求一种方法,通过创建跨设计层的整体技术来实现计算芯片改进的可变部分。重点是解决早期工作的关键限制,例如大开销、有限的电压可伸缩性、隐藏的最坏情况设计实践和新的变化源,以便芯片可以监控变化并动态适应它们。特别是,该项目将追求低开销、电压可扩展的错误检测和纠正方案、使用10-100倍小的传感器结构的细粒度芯片上温度监控,以及为适应芯片老化效应而进行的现场自我测试。研究结果将对高性能、云、移动、嵌入式和无处不在的计算系统产生影响,所有这些系统都受到变化性的严重限制。
英文摘要
The goal of this CAREER project is to address deepening variability challenges in today's computing chip design. Over the last four decades, semiconductor technology has enjoyed rapid advancement, making computing chips the major workhorse for our information age. Continued efforts are ongoing for further improvements, and yet scientists and engineers have recently observed a diminishing return on the research efforts. One of the main causes for this is the ever-growing variability in circuit performance within a chip, from chip to chip, and over the lifetime of the chip. While conventional design practices have ignored the variability aspect for performance improvement, this aspect has now become too compelling and it is prohibitive to simply discard it. The project will essentially address this issue. The project also entails education/outreach plans targeting middle/high-school, undergraduate, and graduate students as well as working professionals within the current framework.More specifically, the project will seek a way to reap the variable portion of improvement in computing chips by creating holistic techniques across design layers. The focus is to address the critical limitations of earlier efforts, e.g., large overhead, limited voltage-scalability, hidden worst-case design practices, and new variation sources, so that chips can monitor variations and dynamically adapt to them. Particularly, the project will pursue low-overhead, voltage-scalable error-detection and correction schemes, fine-grained on-chip thermal monitoring with 10-100X smaller sensor fabrics, and in-field self-testing for adapting to chip-aging effects. The results of the research will have an impact across the spectrum of computing systems - high-performance, cloud, mobile, embedded, and ubiquitous - all of which are severely constrained by variability.
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