SBIR Phase II: Low cost, scalable and selective electrochemical metallization process technology

这个小企业创新研究（SBIR）二期项目的更广泛的影响/商业潜力将是通过降低成本和提高3D硅通孔（TSV）互连与电化学、低成本和选择性金属化技术的可扩展性来加速3D集成电路（IC）的大规模采用。通过验证后，3D TSV选择性金属化技术将以TSV金属填充、凹凸和再分布层形成的选择性电化学金属化技术取代昂贵的damascene互连技术，从而以更低的成本制造高性能的3D微系统。该项目的成功完成将加速3D IC晶圆技术应用于下一代智能手机等最先进的高性能数字设备，从而产生重大的社会影响。该项目还将通过创造美国半导体就业机会和保持美国在广泛的电子应用和消费电子设备方面的技术领先地位，产生积极的经济影响。这个小型企业创新研究（SBIR）二期项目推进了一种新的三维硅通孔（TSV）选择性金属化技术，以制造低成本和可扩展的3D集成电路（IC）。二维缩放的物理和经济限制(所谓的“摩尔？这些挑战刺激了3D TSV技术（所谓的“超过摩尔”）的发展，以提高设备的速度和带宽，以及减少集成微系统的外形因素和功耗。然而，3D集成电路的大规模采用受到3D TSV互连的高成本（由于使用昂贵的气相沉积和化学-机械腐蚀工艺）和其可扩展性差（由于物理和化学气相沉积薄膜的一致性低）的限制，高宽高比和较小的通孔尺寸。在第一期项目中开发的专有3D TSV选择性金属化技术将进一步优化和验证生产工具，以解决3D TSV互连的成本和可扩展性问题。启用低成本和可扩展的3D ic将允许下一代智能手机和其他消费电子设备的异构系统集成。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be to accelerate the mass-scale adoption of 3D integrated circuits (IC) by decreasing the cost and increasing the scalability of 3D through-silicon vias (TSV) interconnects with electrochemical, low cost and selective metallization technology. After its qualification, 3D TSV selective metallization technology will enable fabrication of high performance 3D microsystems at lower cost by replacing costly damascene interconnect technology with selective electrochemical metallization technology for TSV metal fill, bump and redistribution layer formation. The successful completion of this project would have a significant societal impact by accelerating 3D IC wafer technology adoption into state-of-art high performance digital devices such as next generation of smart phones. This project will also have positive economic impact by creating US semiconductor jobs and maintaining US technology leadership over a wide range of electronic applications and consumer electronic devices. This Small Business Innovation Research (SBIR) Phase II project advances a novel three-dimensional through-silicon vias (TSV) selective metallization technology to fabricate low cost and scalable 3D integrated circuits (IC). Physical and economical limitations for two-dimensional scaling (so called "Moore?s Law") prevent further increase of integration density to improve the performance of IC. These challenges have stimulated the development of 3D TSV technology (so called "More than Moore") in order to increase the speed and bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the mass adoption of 3D IC is limited by the high cost of 3D TSV interconnects (due to the use of expensive vapor deposition and chemical-mechanical damascene processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high aspect ratios and smaller via sizes. Proprietary and patented 3D TSV selective metallization technology developed during Phase I project will be further optimized and qualified on production tools to address cost and scalability issues of 3D TSV interconnects. Enabling low cost and scalable 3D ICs will allow heterogeneous systems integration for next generation smart phones and other consumer electronic devices.