CSR: Small: Collaborative Research: Leveraging Intra-chip/Inter-chip Silicon-Photonic Networks for Designing Next-Generation Accelerators

十多年前，GPU是围绕管道构建的固定功能处理器，专用于渲染3D图形。在过去的十年中，随着GPU提供大规模并行计算的潜力变得越来越明显，软件社区开发了新的编程环境（CUDA和OpenCL）来利用这些大规模并行设备。如今，领先的图形供应商通过提供更高的计算吞吐量，为通用高性能计算量身定制GPU设计。虽然GPU能够通过启动大量线程来提供高计算吞吐量，但存储器带宽和系统功率仍然是许多应用程序的限制性约束。 该项目旨在探索使用硅光子链路技术来设计未来GPU/APU系统中的芯片内和芯片间网络，以解决内存带宽限制。特别地，我们将研究硅光子网络有效地支持异构设计的存储器层次结构的潜力，该异构设计集成了CPU和GPU（即，加速处理单元（APU））共享相同的存储器地址空间。为此，使用最先进的基于周期的模拟器，我们将评估一系列内存层次结构和芯片内/芯片间硅光子网络架构，同时运行一组要求高内存带宽的工作负载。此外，这项工作将探索利用硅光子网络的高带宽密度和低延迟来构建可以提供更好计算吞吐量的下一代APU设备的限制和机会。预计这项研究的结果将清楚地证明在GPU和APU设备的存储器层次结构中使用硅光子芯片内/芯片间网络的优势。为了促进和维持APU和硅光子网络这一领域的研究，将向更广泛的加速器/网络研究社区提供支持芯片内和芯片间硅光子网络的开源模拟器。在更广泛的层面上，这项工作弥合了异构系统社区与片上/片外网络社区之间的差距，并为教育和推广提供了多种机会。

A little over a decade ago, GPUs were fixed-function processors built around a pipeline, dedicated to rendering 3-D graphics. In the past decade, as the potential for GPUs to provide massive compute parallelism became apparent, the software community developed new programming environments (CUDA and OpenCL) to leverage these massively parallel devices. Today, the leading graphics vendors tailor their GPU designs for general-purpose high-performance computing by providing higher compute throughput. While GPUs are able to provide high computational throughput by launching a large number of threads, memory bandwidth and system power continue to be limiting constraints for a number of applications. This project proposes to explore the use of silicon-photonic link technology to design the intra-chip and inter-chip networks in future GPU/APU systems with the goal of addressing the memory bandwidth constraint. In particular, we will investigate the potential of the silicon-photonic networks to efficiently support the memory hierarchy of a heterogeneous design, which integrates a CPU and a GPU (i.e., an Accelerated Processing Unit (APU)) that share the same memory address space. To this end, using state-of-the-art cycle-based simulators, we will evaluate a range of memory hierarchies and intra-chip/inter-chip silicon-photonic network architectures while running a demanding set of workloads that require high memory bandwidth. Additionally, this work will explore the limits and opportunities to leverage the high-bandwidth density and low latency of the silicon-photonic networks to architect the next generations APU devices that can provide better compute throughput. It is anticipated that the results of this research will clearly demonstrate the advantages of using silicon-photonic intra-chip/inter-chip networks in the memory hierarchy of GPU and APU devices. To catalyze and sustain research in this area of APUs and silicon-photonic networks, an open-source simulator that supports intra-chip and inter-chip silicon-photonic networks will be made available to the wider accelerator/networking research communities.At a broader level, this work bridges the gap between the heterogeneous systems community and the on-chip/off-chip networks community and opens multiple opportunities for education and outreach.