AitF: EXPL: Data Management in Domain Wall Memory-based Scratchpad for High Performance Mobile Devices

为了在智能手机等移动设备中实现可扩展的性能改进，集成更大更快的内存非常重要。使用传统存储技术扩大片上存储器的主要限制是尺寸和能源效率。尺寸是一个问题，因为设备必须天生小巧才能移动。能源效率是一个问题，因为电池寿命通常是移动设备有用性的限制因素，而智能手机等移动设备中的内存子系统可以消耗大约三分之一的总能量。由于这些限制，移动设备（如智能手机）中每个处理器的内存量在过去几代技术中一直保持相对稳定。在移动设备中结合Domain Wall Memory这一新兴技术是很有吸引力的，因为它比任何竞争技术都能以更小的体积存储更多的信息，同时消耗更少的能量，并且几乎和传统存储技术一样快。但是，Domain Wall Memory具有与传统内存技术不同的物理特性，这可能会影响性能。特别地，域墙内存被分成轨道，就像磁带一样，只能按顺序访问。因此，访问存储在同一轨道中相距很远的两个数据项将是一项昂贵且耗时的操作。因此，获得Domain Wall Memory的最佳性能将需要算法/解决方案，这些算法/解决方案将巧妙地管理数据项到内存中的位置，以便Domain Wall Memory的顺序访问属性不会显着降低性能。该项目的目标是设计、分析、测试和部署算法/解决方案，以解决在移动设备中采用Domain Wall Memory所产生的数据分配问题。由于这些数据管理问题具有独特的特征，因此这些问题的算法开发可能需要开发新的算法设计和分析技术。开发这些算法的良好实际实现，或受这些算法启发的实现，将需要对实现问题和常见实例属性都有重要的理解。该项目将在计算机体系结构和算法领域对学生进行交叉训练。将通过合作和访问向该行业转让技术。将Domain Wall Memory作为一种软件控制的刮刮板存储器，已被广泛应用于嵌入式系统中，以实现高性能和节能。对于在同一Domain Wall Memory轨道中分配的数据项，访问从移动磁头以下的目标域开始，这类似于访问磁带和硬盘驱动器等顺序访问内存。访问数据项的开销包括读/写开销和移位开销。虽然前者是恒定的，但后者在很大程度上取决于数据项在轨道内的分配方式。因此，优化DWM-SPM的聚合访问时间主要涉及最小化移位。DWM-SPM的性能将受到以下策略的显著影响：(a)轨道管理：数据项如何在轨道内组织/排序，(b)数据布局：数据项如何分配到轨道，以及(c)数据选择：如何选择将存储在DWM-SPM中的数据项。该项目将设计并正式分析领域墙存储器理想化模型中的轨迹管理、数据布局和数据选择算法。形式算法的优势在于形式目标可以推动非直观算法的发现。在进行理论研究的同时，将创建一个模拟环境来测试所提出的管理域墙内存的解决方案。这包括硬件建模工具的组装、软件模拟器和基准程序的集合。项目将开发并实现一些简单的策略，作为比较的基线，并获得那些在实践中出现的测试实例的代表，并将理论见解转化为实际实现。然后将这些实现与基线和贪心启发式解决方案进行比较。

To achieve scalable performance improvement in mobile devices such as smart phones, it is important to integrate a larger and faster memory. The major constraints on enlarging on-chip memory using traditional memory technologies are size and energy efficiency. Size is an issue because devices must inherently be small to be mobile. Energy efficiency is an issue because battery life is often the limiting factor in the usefulness of mobile devices, and the memory subsystem in mobile devices such as smart phones can consume about a third of the total energy. Because of these limitations, the amount of memory per processor in mobile devices such as smart phones has stayed relatively stable over the last few generations of technologies. The incorporation of the emerging technology of Domain Wall Memory in mobile devices is attractive as it can store more information in less volume than any competing technologies, while simultaneously using little energy, and being nearly as fast as traditional memory technologies.However, Domain Wall Memory has physical properties that are different than traditional memory technologies, and that can potentially impact performance. In particular, Domain Wall Memory is divided into tracks, which like a tape, may only be accessed sequentially. Thus accessing two data items stored far apart within the same track will be a costly, time-consuming operation. Thus obtaining the best possible performance of Domain Wall Memory will require algorithms/solutions that will smartly manage the placement of data items into memory so that the sequential access properties of Domain Wall Memory do not significantly degrade performance. The goal of the project is to design, analyze, test and deploy algorithms/solutions for data allocation problems that will arise with the adoption of Domain Wall Memory in mobile devices. As these data management problems have unique features, the development of algorithms for these problems will likely require the development of new algorithmic design and analysis techniques. Developing a good practical implementation of these algorithms, or implementations inspired by these algorithms, will require the development of a significant understanding of both implementation issues and common instance properties. The project will cross-train students in the area of computer architecture and algorithms. Transfer of technology to the industry will bepursued through collaborations and visits.It is promising to incorporate Domain Wall Memory as a software-controlled scratchpad memory, which has been widely adopted in embedded systems for achieving high performance and energy efficiency. For data items allocated in the same Domain Wall Memory track, accesses start with shifting the target domains below the head, which is similar to accesses to sequential access memory such as tape and hard drives. The overhead to access a data item includes both the read/write overhead and the shift overhead. While the former is constant, the latter depends heavily on how the data items are allocated within the track. Thus optimizing aggregate access time in DWM-SPM largely involves minimizing shifts. The performance of DWM-SPM will be significantly affected by the policies used for: (a) Track management: How the data items are organized/ordered within a track, (b) Data layout: How the data items are assigned to tracks, and (c) Data selection: How the data items that will be stored in DWM-SPM are selected.The project will design and formally analyze algorithms for track management, data layout, and data selection in idealized models of Domain Wall Memory. The advantage of formal algorithmics is that the formal objective can drive the discovery of non-intuitive algorithms. Concurrent with this theoretical investigation, a simulation environment will be created to test proposed solutions to managing Domain Wall Memory. This includes the assembly of hardware modeling tools, software simulators, and a collection of benchmark programs. The project will develop and implement some simple policies to serve as a baseline to compare against, and obtain test instances representative of those that would arise in practice, and will transfer the theoretical insights into actual implementations. These implementations would then be compared to the baseline and greedy heuristic solutions.