XPS: EXPL: Cache Management for Data Parallel Architecture

当前计算机科学和其他学科的发展依赖于数据并行架构（如GPU）的巨大计算能力。编程数据并行架构并不容易，因为它需要有效处理数千个处理核心的内存层次结构中的数据移动。迄今为止，数据移动问题主要在单核和多核编程系统中进行研究。 因此，转向众核编程范式提出了以下新挑战：1）可扩展性，2）软件和硬件接口，以及3）解决性能和能量之间的权衡。首先，单核和多核处理器中的数据移动模型不能很好地扩展，因此，本项目开发了可扩展的分析模型，但在实践中提供了强大的算法。其次，重新定义软件和硬件的责任很重要。鉴于众核架构的复杂性，不可能使用仅软件或仅硬件的方法来解决数据移动问题。该项目采用跨栈设计原则优化数据移动，旨在联合收割机结合软件和硬件的优势。第三，以前的研究集中在性能上，而没有太多考虑功率和能源效率的问题。该项目以性能和能源为目标，对数据移动的能源成本进行建模，并将此信息集成到整个系统的功率/能源模型中。总的来说，这个项目可以帮助塑造未来的软件-硬件缓存接口，并为下一代缓存系统的设计奠定基础。

Current advances in computer science and other disciplines rely on the massive computation horsepower of data parallel architectures, such as GPUs. Programming data parallel architecture is not easy, as it requires the efficient handling of data movements across the memory hierarchy of thousands of processing cores. To date, data movement problems have been primarily studied in uni-core and multi-core programming systems. Thus, shifting to a many-core programming paradigm presents the new challenges of 1) scalability, 2) software and hardware interface, and 3) addressing the trade-off between performance and energy. First, the data movement models in uni-core and multi-core processors do not scale well, thus, this project develops scalable analytical models and yet provides powerful heuristics in practice. Second, it is important to redefine the responsibilities of software and hardware. Given the complexity of many-core architecture, it is impossible to solve data movement problems using software-only or hardware-only approaches. This project optimizes data movements with a cross-stack design principle that aims to combine the strengths of software and hardware. Third, previous studies have focused on performance without much consideration to issues of power and energy efficiency. This project targets both performance and energy, models the energy cost of data movement and integrates this information into the power/energy model for the entire system. Overall, this project can help shape future software-hardware cache interfaces and lay the foundation for the design of next-generation cache systems.