XPS: EXPL: Cache Management for Data Parallel Architecture

当前计算机科学和其他学科的进步依赖于数据并行体系结构(如GPU)的海量计算能力。编程数据并行体系结构并不容易，因为它需要高效地处理跨越数千个处理核心的内存层次结构的数据移动。到目前为止，数据移动问题主要是在单核和多核编程系统中进行研究的。因此，转向多核编程范例带来了新的挑战：1)可伸缩性，2)软件和硬件接口，以及3)处理性能和能量之间的权衡。首先，单核和多核处理器中的数据移动模型不能很好地扩展，因此，本项目开发了可扩展的分析模型，但在实践中提供了强大的启发式方法。其次，重要的是重新界定软件和硬件的责任。考虑到多核体系结构的复杂性，不可能使用纯软件或纯硬件方法来解决数据移动问题。该项目采用旨在结合软件和硬件优势的跨堆栈设计原则来优化数据移动。第三，以前的研究侧重于性能，而没有太多地考虑功率和能效问题。该项目以性能和能源为目标，对数据移动的能源成本进行建模，并将此信息集成到整个系统的电力/能源模型中。总体而言，该项目可以帮助塑造未来的软硬件缓存接口，并为下一代缓存系统的设计奠定基础。

Current advances in computer science and other disciplines rely on the massive computation horsepower of data parallel architectures, such as GPUs. Programming data parallel architecture is not easy, as it requires the efficient handling of data movements across the memory hierarchy of thousands of processing cores. To date, data movement problems have been primarily studied in uni-core and multi-core programming systems. Thus, shifting to a many-core programming paradigm presents the new challenges of 1) scalability, 2) software and hardware interface, and 3) addressing the trade-off between performance and energy. First, the data movement models in uni-core and multi-core processors do not scale well, thus, this project develops scalable analytical models and yet provides powerful heuristics in practice. Second, it is important to redefine the responsibilities of software and hardware. Given the complexity of many-core architecture, it is impossible to solve data movement problems using software-only or hardware-only approaches. This project optimizes data movements with a cross-stack design principle that aims to combine the strengths of software and hardware. Third, previous studies have focused on performance without much consideration to issues of power and energy efficiency. This project targets both performance and energy, models the energy cost of data movement and integrates this information into the power/energy model for the entire system. Overall, this project can help shape future software-hardware cache interfaces and lay the foundation for the design of next-generation cache systems.