SBIR Phase II: A hardware FPGA implementation of H.265/HEVC low latency video encoder algorithms for professional applications

小型企业创新研究(SBIR)第二阶段项目的更广泛影响/商业潜力是促进和改善普通公众每天使用的产品中高质量视频的使用。从高分辨率自动仪表盘摄像头，到飞行无人机的低延迟视频流，到无线笔记本电脑扩展底座，到更高质量的新闻和体育赛事报道，再到更好、更快的互联网视频传输，每一种应用都需要本项目将开发的高质量、低延迟、灵活、高能效的视频编码器。视频的使用每天都在增加。视频指导手册正在取代印刷的指导手册。视频正在取代在线广告、社交媒体和广告牌中的静止图像。据预测，在未来几年内，90%以上的互联网流量将是视频数据。启用所有这些应用程序需要视频压缩方面的最新技术，例如本项目中开发的技术。该小型企业创新研究(SBIR)第二阶段项目解决了使用最新的H.265压缩技术创建实时视频编码器的问题，该编码器在FPGA(现场可编程门阵列)上以硬件运行。FPGA是一种芯片，其上的逻辑是可配置的--它可以被编程以实现任何功能。它代表了专用集成电路和纯软件解决方案之间的中间点，前者开发成本非常高，而且一旦制造就无法更改或增强，后者非常灵活，但需要庞大且耗电的设备(即计算机)作为底层平台。根据这项拨款进行的研究将设计、测试和实施易于在现场可编程门阵列上实现的算法，这些算法实时运行，并根据所使用的比特数产生高质量的压缩视频的视觉质量。在本研究的结论中，我们的目标是展示一个运行在一片FPGA上的功能性HEVC/H.265编码器，它在成本、灵活性、功耗和性能上都比其他编码器更具优势。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to promote and improve the use of high quality video in products that the general public works with every day. From high resolution auto dashboard cameras, to low latency video streams from flying drones, to wireless laptop docking stations, to higher quality coverage of news and sporting events, to better and faster delivery of video over the Internet, every application requires the high quality, low latency, flexible, power efficient video encoders that will be developed in this project. The uses of video are increasing every day. Video instruction manuals are replacing printed instruction manuals. Video is replacing still images in on-line advertising, social media and billboards. It is predicted that over 90% of all Internet traffic will be video data in the next few years. Enabling all these applications requires the latest technology in video compression such as the techniques developed in this project.This Small Business Innovation Research (SBIR) Phase II project tackles the problem of creating a real time video encoder, using the latest H.265 compression technology, running in hardware on an FPGA (Field Programmable Gate Array). An FPGA is a type of chip on which the logic is configurable - it can be programmed to implement any function. It represents a mid-point between a dedicated integrated circuit, which is very expensive to develop, and can never be changed or enhanced once it is fabricated, and a pure software solution which is very flexible but requires bulky and power hungry equipment (i.e. computers) as an underlying platform. The research conducted under this grant will devise, test, and implement algorithms that are amenable to realization on an FPGA, that operate in real time, and that yield a high quality result in terms of the visual quality of the compressed video with respect to the number of bits used. The goal, at the conclusion of this research, is the demonstration of a functional HEVC/H.265 encoder running on an FPGA which has cost, flexibility, power and performance advantages over other encoders.