SBIR Phase II: Area and Energy Efficient Error Floor Free Low-Density Parity-Check Codes Decoder Architecture for Flash Based Storage

这个小型企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力将是闪存的高性能纠错。纠错在使数字设备可靠方面起着至关重要的作用。缩小半导体几何形状会导致更多的错误。这为闪存造成了一个特殊的问题，其中对更严格的纠错的需求接近广泛使用的Bose Chaudhuri Hocquengham纠错的实际极限。低密度奇偶校验（LDPC）是一种公认的解决方案，可以接近可能的理论极限。这种基于LDPC的技术可以在不增加现有BCH解决方案的成本的情况下提高闪存的寿命。这项技术帮助闪存企业使用更高密度的闪存来提高存储容量，降低存储产品成本。如果没有LDPC技术的上级性能、小尺寸和低功耗，向低成本高容量闪存的迁移将严重放缓。在缺乏类似替代方法的情况下，大量依赖于高度可靠和经济的闪存存储的产品的性能将受到严重限制。这个小型企业创新研究（SBIR）第二阶段项目将使用各种技术来最大限度地减少面积和功耗要求，并提高闪存低密度奇偶校验（LDPC）纠错码的性能。这些技术中的许多可应用于从WiFi到硬盘驱动器的数字通信和存储中的广泛纠错应用。对更好的错误校正的需要对于闪存是至关重要的，但是存在对改进的错误校正的日益扩大的需求。例如，较大的存储器需要更好的纠错，以确保系统故障率较低。在接下来的两年内，该公司预计将开发一个Verilog版本的LDPC解码器，可以很容易地与闪存控制器集成。该项目将与潜在客户/合作伙伴合作，以确保代码与控制器一起工作。从长远来看，随着对更可靠数据的需求继续迅速扩大，这些技术可以适用于广泛的应用。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be high performance error correction for flash memory. Error correction plays a critical row in making digital devices reliable. Shrinking semiconductor geometries results in more errors. This has created a special problem for flash memory where the need for more rigorous error correction is approaching a practical limit with the widely used Bose Chaudhuri Hocquengham error correction. Low Density Parity Check (LDPC) is a recognized solution that can approach the theoretical limits of what is possible. This LDPC based technology can improve lifetime of flash by without the added cost of the existing BCH solution. This technology helps Flash Memory enterprises to use higher density flash to improve storage capacity and cut the storage product costs. Without the superior performance, small size and low power consumption of the LDPC technology, the migration to low cost high capacity flash memories will be seriously slowed. In the absence of a comparable alternative approach, there will be serious limitations on the performance of a vast array of products that depend on highly reliable and economical flash storage.This Small Business Innovation Research (SBIR) Phase II project will use a variety of techniques to minimize the area and power requirements and enhance the performance of Low Density Parity Check (LDPC) error correction codes for flash memory. Many of these techniques are applicable to a wide range of error correction applications in digital communication and storage from WiFi to hard disk drives. The need for better error correction is crucial for flash memory but there is a widening demand for improved error correction. For example larger memories require better error correction to insure the system failure rate is low. In the next two years the company expects to develop a Verilog version of the LDPC decoder that is easily integrated with a flash controller. The project will work with potential customers/partners to ensure the code works with controllers. In the long run these techniques can be adapted to a wide range of applications as the need for more reliable data continues to rapidly expand.