SBIR Phase I: An Automated Design Flow to Build Energy Efficient Vision Processing and Machine Learning Chips for the Internet of Things

这个小企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力将是将数据驱动的决策带到人类与技术互动的新领域。物联网（IoT）包含硬件、软件和系统，能够以电子方式监控和管理物理世界中的对象。物联网设备将实现系统和流程的性能优化，为人们和企业节省时间，并改善生活质量。到2025年，物联网的总经济影响估计将超过11万亿美元。然而，达到这些崇高的估计需要硬件技术的进步，特别是对于能源受限的物联网设备，这些设备必须收集数据，根据收集的数据做出决策，并在有限的功率预算下与更大的系统通信。该公司将开发低功耗嵌入式计算机视觉系统和机器学习算法，用于虚拟/增强现实、无人机、监控摄像头和其他应用。 拟议的项目推进新的商业化？时间弹性？芯片技术，通过为物联网设备带来动态电压缩放，对传统设计流程的影响最小，从而保证无与伦比的功率效率。改变器件的工作电压可以显著提高能效，但由于设计时间和复杂性增加，许多电路设计人员没有利用这项技术。该提案的重点是开发一个全面的计算机辅助设计（CAD）流程，将现有的同步设计转换为支持各种电压的更高效的异步时序弹性设计。拟议的项目解决了自动化流程的三个方面：可制造性和测试设计;在较低电压下分析逻辑单元库;以及将新的定时弹性电路与同步电路连接起来。该流程结合了模拟、分析、综合、布局布线和测试，具有与标准商业流程相似的效率。本研究的目的是限制额外的测试开销的转换设计和性能的影响，与传统的电路接口同步同行的10%以内。这种新流程的开发将使芯片设计从根本上更加节能，并有助于将机器学习的全部功能带到更小的外形尺寸中。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project will be to bring data-driven decision making to new areas of human interaction with technology. The Internet of Things (IoT) embodies the hardware, software, and systems that enable monitoring and managing objects in the physical world electronically. IoT devices will enable performance optimization of systems and processes, time savings for people and businesses, and quality of life improvements. The total economic impact of the IoT is estimated to exceed $11 trillion by 2025. However, reaching these lofty estimates requires advances in hardware technology, particularly for energy-constrained IoT devices that must gather data, make decisions based on the data gathered, and communicate to a larger system under a limited power budget. The company will develop low power embedded computer vision systems and machine learning algorithms for use in for virtual/augmented reality, drones, surveillance cameras and other applications. The proposed project advances the commercialization of new ?timing-resilient? chip technology, which promises unparalleled power efficiency by bringing dynamic voltage scaling to IoT devices with minimal impact on traditional design flows. Changing the operating voltage of a device can lead to significant energy efficiency improvements, yet many circuit designers do not take advantage of this technique due to increased design time and complexity. This proposal focuses on the development of a comprehensive computer-aided design (CAD) flow that transforms existing synchronous designs into more efficient asynchronous timing-resilient designs that support a wide range of voltages. The proposed project addresses three aspects of the automated flow: design for manufacturability and test; analysis of logic cell libraries at lower voltages; and interfacing the new timing-resilient circuits with synchronous circuits. The flow combines simulation, analysis, synthesis, place-and-route, and test with similar efficiency as standard commercial flows. This research aims to limit the additional testing overhead of the converted design and the performance impact of interfacing with traditional circuits to within 10% of synchronous counterparts. The development of this new flow will enable chip designs that are fundamentally more energy efficient and help bring the full power of machine learning to smaller form factors.