CAREER:Enabling Scalable, Modular, and Efficient Architecture Specialization Fabrics

过去计算机处理器能力的指数级改进现在正受到物理设备技术进展长期放缓的威胁。另一种方法是为一小部分任务专门设计处理器，为了提高性能和能效而牺牲通用性。然而，如果过度依赖硬件专业化，新的快速发展的应用程序的创新步伐将被扼杀。因此，需要新的技术来平衡专用处理器的效率和通用处理器的有用性之间的基本权衡。一个有前途的发展方向是开发专门化结构，其中软件接口和硬件实现是共同设计的，以使具有广泛应用特征的程序能够有效执行。这一职业奖发展了制造这种面料背后的原则，解决了它们面临的两个主要挑战。第一个是可伸缩性：如何在不降低专门化的好处的情况下支持大量的计算单元。第二个是模块化：如何通过可组合的硬件根据特定的设计设置(例如，针对数据中心机器、电话或可穿戴设备)实现织物的简单定制。这项工作的广泛潜力是使有原则的专门硬件能够通过传播已发现的原则和通过硬件和软件的开放源码版本继续带来指数级的性能和能量改进。对于行业来说，开发的框架可以使硬件公司利用为其用例量身定做的零设计工作硬件。对于学术界来说，这些可以降低硬件/软件协同设计研究的进入成本，使研究人员更容易进行跨领域的创新。这一框架正在整合到课程中，教授硬件和软件之间的基本交互。总体而言，这项工作的广泛目标是创建可编程的加速器结构，可扩展到高吞吐量，其功能可以模块化组合-最终在许多领域实现类似加速器的性能和能效。在智力上，它进一步统一了计算机体系结构的两个不同领域，即研究片上存储系统和研究体系结构专业化。该项目通过两次推进开发了可扩展和模块化的专业化结构的原则。第一部分探讨了如何利用高级ISA结构来重新考虑专用结构的高速缓存层次结构和片上通信网络的设计，这些结构通常受通信带宽或访问/存储能量的限制。关键的创新是向内存系统公开一组更高级别的抽象，描述内存访问的粗粒度模式。利用该信息可以减少通信和标签/冗余高速缓存访问的低效，但需要对现有协议进行重大改造以保持简单的存储器语义。第二个推力开发了一个框架，用于组合模块化体系结构功能，以支持针对非常不同的应用程序领域的琐碎硬件定制。关键的创新是高级ISA功能的开发，这些功能直接对应于可组合的硬件结构。这一努力为构成ISA暴露的微体系结构功能开发了模板设计和指令集描述，探索了一组适用于常规和非常规工作负载的ISA功能，并开发了一个编译器来隐藏ISA的复杂性。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Past exponential improvements to computer processor capabilities are now being threatened by a long-term slowdown of the progress in physical device technologies. An alternate approach is to specialize processor design for a small set of tasks, sacrificing generality for improved performance and energy-efficiency. However, if hardware specialization is relied on too much, the pace of innovation for new and fast-moving applications will be stifled. Hence, new techniques are required to balance the fundamental trade-offs between the efficiency of specialized processors with the usefulness of general processors. A promising way forward is the development of specialization fabrics, where the software interface and hardware implementation are co-designed to enable efficient execution of programs with broad application characteristics. This CAREER award develops the principles behind building such fabrics, addressing their two main challenges. The first is scalability: how to support vast amounts of computational units without mitigating the benefits of specialization. The second is modularity: how to enable simple tailoring of the fabric to a particular design setting (e.g. for a datacenter machine, phone, or wearable) through composable hardware. The broad potential of this work is to enable principled specialized hardware which can continue to bring exponential performance and energy improvements, both through dissemination of discovered principles and through open source releases of hardware and software. For industry, the developed frameworks can enable hardware companies to leverage zero-design-effort hardware tailored for their use cases. For academia, these can lower the cost of entry of hardware/software co-design research, and enable researchers to make cross-domain innovations more easily. This framework is being integrated into courses to teach the fundamental interactions between hardware and software.Overall, the broad goal of this work is to create a programmable accelerator fabric, scalable to high throughput, and whose features can be modularly composed - ultimately enabling accelerator-like performance and energy efficiency across many domains. Intellectually, it furthers the unification of two disparate fields of computer architecture, the study of on-chip memory systems and the study of architectural specialization. The project develops the principles of scalable and modular specialization fabrics through two thrusts. The first explores how to leverage high-level ISA constructs to rethink the design of the cache hierarchy and on-chip communication network for specialization fabrics, which are typically constrained by communication bandwidth or access/storage energy. The key innovation is to expose to the memory system a set of higher level abstractions describing coarse-grain patterns of memory access. Leveraging this information can reduce the inefficiencies of communication and tag/redundant cache access, but requires a significant overhaul to existing protocols to maintain simple memory semantics. The second thrust develops a framework for composing modular architecture features to enable trivial hardware customization for vastly different application domains. The key innovation is the development of high-level ISA features which have a direct correspondence to composable hardware structures. This thrust develops a template design and instruction-set description for composing ISA-exposed microarchitecture features, explores a set of ISA features for regular and irregular workloads, and develops a compiler to hide ISA complexity.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.