Detection and adaptive prioritization of semi-static data streams and traffic patterns in Network-on-Chips

本课题的目的是设计和实现一种流量自适应的片上网络，以减少复杂多核系统中的通信延迟。应在线检测功能单元之间的临时恒定通信模式，并通过绕过完整的路由器管道，无延迟地传输相应的数据流。这种暂时不变的模式在多功能系统中的应用程序运行期间存在，在具有分布式缓存的多核处理器系统中也存在。适当数据流的优先级将应用于两个功能单元之间的单个半静态数据流，以及半静态数据流的重复模式。流量模式检测由每个路由器在本地完成，并且只考虑一个路由器输入的所有数据流的本地路由决策。这允许具有不同目的地址和虚拟通道标识符的几个独立数据流的本地聚合。如果几个连续的路由器优先级相同的聚合，则建立直接点对点连接。根据实际的流量模式，这将导致面向分组和电路交换片上网络的结合。半静态数据流的发生频率、持续时间和模式不仅取决于功能块之间的通信特性及其位置，还取决于所采用的路由算法。因此，需要评估不同的确定性路由算法和自适应路由算法对这些参数的影响。它还打算使用自适应路由算法来支持半静态数据流聚合的形成。自适应和容错路由算法也将用于限制阻塞网络链路对非优先数据流的影响，因为它们只用于半静态数据流。非优先级数据流需要重新路由，以便优先级连接能够尽可能长时间地维持。片上网络架构专门用于ASIC设计以及部分可重构的FPGA设计。性能、能耗和硬件要求将对两种设计方案进行评估。在项目结束时，将通过基于fpga的测试系统来验证片上网络架构的有效性。

Aim of this project is the design and implementation of a traffic adaptive network-on-chip for communication latency reduction in complex manycore systems. Temporally constant communication patterns between functional units should be detected online and the corresponding data streams should be transferred without any delay by bypassing the complete router pipeline. Such temporally constant patterns exist for the duration of an application in multifunctional systems as well as temporally in manycore processor systems with distributed caches. Prioritization of suitable data streams will be applied to individual semi-static data streams between two functional units, as well as to repeating patterns of semi-static data streams. Traffic pattern detection is done locally by each router and only accounts the local routing decisions for all data streams of one router input. This allows local aggregation of several individual data streams with different destination addresses and virtual channel identifiers. If several consecutive routers prioritize the same aggregate, a direct point-to-point connection is set up. Depending on the actual traffic patterns this results in a combination of a packet-oriented and a circuit switched network-on-chip.The frequency of occurrence, duration and pattern of semi-static data streams do not only depend on the communication characteristics between functional blocks and their location, but also on the routing algorithm used. Therefore the effect of different deterministic and adaptive routing algorithms on these parameters needs to be evaluated. It is also intended to use adaptive routing algorithms to support the formation of aggregates of semi-static data streams. Adaptive and fault-tolerant routing algorithms will also be used to limit the effects of blocked networks links for non-prioritized data streams due to their exclusive use for semi-static data streams. Non-prioritized data streams need to be rerouted in such a way that prioritized connections can be sustained as long as possible. The network-on-chip architecture is dedicated for the use in ASIC designs as well as in partially reconfigurable FPGA designs. Performance, energy consumption and hardware requirements will be evaluated for both design alternatives. At the end of the project, the effectiveness of the network-on-chip architecture will be demonstrated by means of an FPGA-based test system.