SPX: Collaborative Research: Harnessing the Power of High-Bandwidth Memory via Provably Efficient Parallel Algorithms

许多并行科学应用的一个重要瓶颈是内存性能。最近，供应商已经推出了一种称为高带宽内存（HBM）的新内存来缓解这一瓶颈。该项目将为使用HBM开发算法基础。该项目具有广泛的经济、技术和科学影响的潜力，因为工业界对这项技术进行了投资，而且许多国家的战略代码都在具有hbm功能的机器上运行。pi将通过培训博士、硕士和荣誉项目的学生，在包括算法设计、高性能软件和处理器架构在内的交叉问题上，将研究与研究生和本科水平的教育结合起来。供应商提供的新方法是将内存（HBM）直接绑定到处理器芯片上，这允许更多的连接，从而实现更高的带宽。虽然新存储器的大小比现代片上缓存大，但物理限制限制了存储器的容量明显小于DRAM。HBM并不完全适合标准内存层次结构。该项目将培养对如何为HBM增强型架构进行算法设计代码的基本理解。克服这些智力上的挑战，使用HBM实现多核可伸缩性需要新的算法、模型和抽象，由研究硬件问题、高性能计算挑战和理论建模和分析的研究人员之间的合作带头。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

An important bottleneck for many parallel scientific applications is memory performance. Recently, vendors have introduced a new memory called high-bandwidth memory (HBM) as an approach to alleviate this bottleneck. This project will develop an algorithmic foundation for using HBM. The project has the potential for a broad economic, technological, and scientific impact, since industry has an investment in this technology and many of the nation's strategic codes are being run on HBM-capable machines. The PIs will integrate research with education at the graduate and undergraduate levels by training PhD, MS, and honors program BS students in cross-cutting issues encompassing algorithm design, high-performance software, and processor architecture. The new approach offered by vendors is to bond memory (HBM) directly to the processor chip, which allows for more connections, enabling higher bandwidth. Although the size of the new memory is larger than modern on-chip caches, physical constraints limit the capacity of the memory to be significantly smaller than DRAM. HBM does not cleanly fit in the standard memory hierarchy. This project will develop a foundational understanding of how to algorithmically design codes for HBM enhanced architectures. Overcoming these intellectual challenges to achieve multi-core scalability using HBM requires new algorithms, models, and abstractions, spearheaded by this collaboration between researchers who study hardware issues, high performance computing challenges, and theoretical modeling and analysis.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.