EAGER: Hot Carrier Effects in Novel Miniaturized Gate-All-Around (GAA) Field Effect Transistors (FETs)

对更小、更高效的电子产品的需求促使商业公司不断突破晶体管的规模极限。对于几十纳米量级的单晶体管来说，器件已经从2D范式进入了3D范式。高度小型化的器件引入了可靠性问题，如热载流子注入，其中不受欢迎的大电流导致整体寿命下降和性能差。工程师经常使用仿真工具来理解器件中的热载子效应。为了减少复杂性和模拟时间，这些工具抽象了许多详细的物理，这些物理对于今天使用的复杂和小型化的新设备是必要的。这项工作将使用一种新颖的3D模拟方法，能够捕获必要的详细物理建模下一代设备。了解这些设备故障的物理原理，最终将为最终用户带来更小、更便宜、更可靠的电子产品。这项工作也有可能影响我们对互补设备（如led、太阳能电池等）的理解，并对可再生能源行业产生影响，从而为世界各地的消费者提供更多负担得起、可靠和清洁的能源。这项工作将使用具有全频段功能的蒙特卡罗代码套件来执行门全能场效应晶体管中热载流子注入的第一个3D模型。Anduril可能被证明是现代3D微型化技术设备模拟工具的下一个黄金标准。三维模拟热载流子注入堆叠栅极晶体管将比较实验表征提出了这项工作。PI可以访问imec的垂直堆叠栅全能晶体管，这些晶体管已被证明具有接近理想的亚阈值斜率（~67 mV/dec）。用PI吗？作为第二职位，她有能力招聘研究生人才，并可以使用范德比尔特大学辐射和可靠性小组的全套可靠性测试设备。直流应力条件和1/f噪声测量将在范德比尔特大学PI的指导下进行。此外，使用Anduril代码套件的模拟将使用ACCRE超级计算集群进行。模拟将分阶段进行，从单栅极全能晶体管开始，其可靠性已经过实验研究，最终是堆叠栅极全能架构，其可靠性尚不清楚。PI提出的工作是及时和相关的，因为目前的趋势是垂直堆叠栅极全方位晶体管，并且在理解这些器件中驱动热载流子退化的故障物理方面仍然存在巨大的知识空白。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The demand for smaller, more efficient electronics has driven commercial companies to push the limits of scaling for transistors. Devices have moved from the 2D paradigm into the 3D paradigm for single transistors on the order of tens of nanometers. Highly miniaturized devices introduce reliability concerns such as hot carrier injection, where large undesirable currents lead to overall lifetime degradation and poor performance. Engineers often use simulation tools to understand hot carrier effects in devices. In order to reduce complexity and simulation time these tools abstract away much of the detailed physics which is necessary for the complex and miniaturized novel devices used today. This work will use a novel 3D simulation approach that is able to capture the necessary detailed physics for modeling the next- generation of devices. Understanding the physics of failure for these devices will ultimately lead to smaller, cheaper and more reliable electronics for the end user. This work also has the potential to impact our understanding of complimentary devices (e.g. LEDs, Solar Cells, etc.) and has implications for the renewable energy industry, resulting in increased access to affordable, reliable and clean energy to consumers around the world.This work will use a Monte Carlo code suite with full-band capabilities to perform the first of its kind 3D model of hot carrier injection in gate-all-around field effect transistors. Anduril could prove to be the next gold standard of device simulation tools for modern 3D mianiaturized technologies. 3D simulations of hot carrier injection in stacked gate-all-around transistors will be compare to experimental characterization proposed in this work. The PI has access to vertically stacked gate-all-around transistors from imec which have been shown to have near-ideal subthreshold slopes (~67 mV/dec). With the PI?s secondary appointment she has the ability to recruit graduate talent and access to a full suite of reliability testing equipment in the Radiation and Reliability group at Vanderbilt. DC stress conditions and 1/f noise measurements will be conducted under the advisement of the PI at Vanderbilt. Additionally, simulations using the Anduril code suite will be conducted using the ACCRE super- computing cluster. Simulations will occur in phases beginning with a single gate-all-around transistor, whose reliability has been studied experimentally, and ultimately a stacked gate-all-around architecture, whose reliability is less understood. The work proposed by the PI is timely and relevant given the current trends moving to vertically stacked gate-all-around transistors, and the large knowledge gaps that still exist for understanding the physics of failure driving hot carrier degradation in these devices.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.