SPX: Parallel Models and Algorithms for Emerging Memory Systems

随着高度并行的多核（计算）机器的出现，内存在能源使用、组件密度、延迟、带宽和可靠性方面日益成为持续性能改进和可伸缩性的限制因素。为了解决这些问题，半导体行业一直在开发新的字节可寻址非易失性随机存取存储器（NVRAM）技术。与标准动态随机存取存储器（DRAM）相比，这些存储器提供了显著降低能量需求和更高密度的承诺，同时不会因功率损失而失去其状态。然而，在NVRAM技术中，写入内存的操作在吞吐量和能量方面比从内存中读取的操作更昂贵。该项目正在开发和测试基于NVRAM的新兴大型和极端规模计算机系统的新抽象，以及如何有效地利用这种不对称性在大型计算系统中获得更好的性能。重点将放在理论与实践的结合上，并考虑从硬件本身到高级算法和编程模型的多个抽象层次的问题。该项目将包括一个教育部分，将教授学生有关新技术以及如何有效地使用它。该项目由三个主要组成部分组成：(1)开发结合易失性和非易失性存储器的系统的方法，允许单个处理器在允许整个系统正常运行的情况下发生故障；(2)为写操作比读操作更昂贵的设置开发有效的算法和缓存策略；(3)开发利用每个存储器控制器中重要计算能力的技术。在第一个组件中，该项目正在研究如何自动将任意并发程序转换为处理器可能出现故障的设置，以便运行转换后的程序和从故障中恢复的开销都很低。在第二个组成部分中，该项目正在开发通用技术，以减少与读取相比的写入次数，或减少需要写入的内存部分，并将这些技术应用于广泛的算法类别。研究小组将发展理论和实验测量这些技术和算法的有效性。在第三个组件中，该项目正在研究如何使用内存控制器来降低容错成本，并允许较弱的内存模型，目的是扩展到大型系统。一个关键的智力挑战是确保模型、技术和算法同时简单、优雅和实用。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

With the advent of highly-parallel many-core (computing) machines, memory has increasingly become a limiting factor in continued performance improvement and scalability, in terms of energy usage, component density, latency, bandwidth, and reliability. To help deal with these and other problems, the semiconductor industry has been developing new byte-addressable nonvolatile random access memory (NVRAM) technologies. These offer the promise of significantly lower energy needs and higher density than standard dynamic random access memory (DRAM), while not losing their state on power loss. However, in NVRAM technology, operations that write to memory are more costly in terms of throughput and energy than operations that read from memory. This project is developing and testing new abstractions for emerging large and extreme-scale computer systems based on NVRAM, and how to effectively leverage this asymmetry for better performance in large computing systems. The focus will be on combining theory and practice, and considering issues across multiple levels of abstraction, from the hardware itself, to high-level algorithms and programming models. The project will include an educational component that will teach students about the new technology and how to effectively use it.The project consists of three main components: (1) developing methodologies for systems combining volatile and nonvolatile memory that allow individual processors to fail while permitting the overall system to continue correctly, (2) developing efficient algorithms and caching policies for settings where writes are more expensive than reads, and (3) developing techniques to take advantage of the significant computing capability in each memory controller. In the first component, the project is studying how to automatically convert arbitrary concurrent programs into a setting where processors can fail so that the overhead for both running the converted program and recovering from a failure is low. In the second component, the project is developing general purpose techniques to reduce the numbers of writes compared to reads, or reduce the fraction of the memory that needs to be written to, and applying the techniques across a broad class of algorithms. The research team will both develop theory and experimentally measure the effectiveness of these techniques and algorithms. In the third component, the project is looking at how to use the memory controllers to reduce the cost of fault tolerance and allow for weaker memory models, with the purpose of scaling to large systems. A key intellectual challenge is to ensure that the models, techniques, and algorithms are simultaneously simple, elegant, and practical.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.