SBIR Phase II: Chemical Mechanical Planarization pad with controlled micro features for sub 7nm semiconductor technology

这个小企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力是帮助半导体芯片制造商克服化学机械平面化/抛光（CMP）工艺的制造挑战。CMP工艺实现尖端制造；目前，芯片制造商经常面临缩放困难，因为最小特征的尺寸不断减小，增加了CMP缺陷的影响，导致更高的缺陷率。提出的抛光工艺使芯片制造商能够将这些CMP缺陷减少50%并提高性能，同时降低成本并提高工艺吞吐量。这个小企业创新研究（SBIR）二期项目将用创新的抛光垫改进CMP工艺。传统的抛光垫内部有随机分布的微孔，在抛光过程中，通常在垫体和晶圆之间产生约1%的实际接触面积。这将导致不必要的抛光结果，例如由于应力集中在凹凸不平上，在芯片图案上产生盘状/侵蚀和划痕缺陷。传统的护垫需要一个护垫调理过程来恢复护垫表面的凹凸不平。本项目开发的抛光工艺使用微加工技术来控制垫表面的微特征。因此，焊盘和晶圆之间的接触面积是可定制的，可控制高达30%。这将提高抛光性能的精度和一致性，导致更少的缺陷。由于软子衬垫上的微特征是独立的，因此衬垫的整合度增加，晶圆上的压力均匀分布在晶圆表面。这将显著提高芯片级的平整化和晶圆级的均匀性，减少焊盘磨损。因此，衬垫调理过程可以最小化，甚至从CMP过程中消除。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to help semiconductor chipmakers overcome manufacturing challenges in Chemical Mechanical Planarization/Polishing (CMP) processes. CMP processes enable cutting-edge manufacturing; currently chipmakers often face scaling difficulties as the size of the smallest features continues to decrease, increasing the impact of CMP imperfections and resulting in higher defect rates. The proposed polishing process enables chip fabricators to reduce these CMP imperfections by 50% and improve performance, while reducing costs and increasing process throughput. This Small Business Innovation Research (SBIR) Phase II project will improve CMP processes with innovative polishing pads. Conventional polishing pads have randomly distributed micropores inside of the pads and typically generate around 1% real contact area between the pad asperities and wafer during polishing. This leads to unwanted polishing results, such as dishing/erosion and scratch defects on chip patterns due to the stress concentration on asperities. Conventional pads require a pad conditioning process to regenerate the asperities on the pad surface. The polishing processes developed under this project use microfabrication technologies to control micro-features on the pad surface. Therefore, the contact area between the pad and wafer is customizable and controllable up to 30%. This will improve the polishing performance precision and consistency, leading to fewer defects. As the micro-features on the soft sub-pad are independent, the conformity of the pad increases and the pressure on the wafer is evenly distributed across the wafer surface. This will significantly improve the chip-level planarization and wafer-level uniformity, and reduce the pad wear. As a result, the pad conditioning process can be minimized or even eliminated from the CMP process.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.