SBIR Phase II: Chemical Mechanical Planarization pad with controlled micro features for sub 7nm semiconductor technology

这个小型企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力是帮助半导体芯片制造商克服化学机械平坦化/抛光（CMP）工艺中的制造挑战。 CMP工艺使尖端制造成为可能;目前，芯片制造商经常面临缩放困难，因为最小特征的尺寸不断减小，增加了CMP缺陷的影响，导致更高的缺陷率。所提出的抛光工艺使芯片制造商能够将这些CMP缺陷减少50%并提高性能，同时降低成本并提高工艺产量。 这个小型企业创新研究（SBIR）第二阶段项目将使用创新的抛光垫改进CMP工艺。常规的抛光垫在垫内部具有随机分布的微孔，并且在抛光期间通常在垫粗糙体和晶片之间产生约1%的真实的接触面积。这导致不希望的抛光结果，例如由于粗糙体上的应力集中而导致的芯片图案上的凹陷/侵蚀和划痕缺陷。传统的焊盘需要焊盘调节工艺来再生焊盘表面上的粗糙度。在此项目下开发的抛光工艺使用微加工技术来控制抛光垫表面的微特征。因此，焊盘和晶圆之间的接触面积可定制和控制高达30%。这将提高抛光性能的精度和一致性，从而减少缺陷。由于软性子垫上的微特征是独立的，所以垫的一致性增加，并且晶片上的压力均匀地分布在晶片表面上。这将显著改善芯片级平坦化和晶圆级均匀性，并减少焊盘磨损。 该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to help semiconductor chipmakers overcome manufacturing challenges in Chemical Mechanical Planarization/Polishing (CMP) processes. CMP processes enable cutting-edge manufacturing; currently chipmakers often face scaling difficulties as the size of the smallest features continues to decrease, increasing the impact of CMP imperfections and resulting in higher defect rates. The proposed polishing process enables chip fabricators to reduce these CMP imperfections by 50% and improve performance, while reducing costs and increasing process throughput. This Small Business Innovation Research (SBIR) Phase II project will improve CMP processes with innovative polishing pads. Conventional polishing pads have randomly distributed micropores inside of the pads and typically generate around 1% real contact area between the pad asperities and wafer during polishing. This leads to unwanted polishing results, such as dishing/erosion and scratch defects on chip patterns due to the stress concentration on asperities. Conventional pads require a pad conditioning process to regenerate the asperities on the pad surface. The polishing processes developed under this project use microfabrication technologies to control micro-features on the pad surface. Therefore, the contact area between the pad and wafer is customizable and controllable up to 30%. This will improve the polishing performance precision and consistency, leading to fewer defects. As the micro-features on the soft sub-pad are independent, the conformity of the pad increases and the pressure on the wafer is evenly distributed across the wafer surface. This will significantly improve the chip-level planarization and wafer-level uniformity, and reduce the pad wear. As a result, the pad conditioning process can be minimized or even eliminated from the CMP process.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.