SBIR Phase II: Ultra-high Throughput Parallel Optical Links for Chip-to-Chip Interconnects

小型企业创新研究(SBIR)第二阶段项目的更广泛影响/商业潜力是为一般计算机应用创造非常低功率和非常高容量的光互连。计算机性能受到芯片和内存之间连接的速度、功率和延迟的限制。电互连的局限性是众所周知的，而光互连克服了这些限制，提供了100-1000倍的性能改进。虽然光互连在历史上一直受到高成本和高功率的阻碍，但最近的发展表明，光互连的前景可以实际实现。光互连将显著提高企业和云计算服务的整体性能，特别是在数据中心计算机中使用时，同时降低电力消耗。这反过来将大大提高资源利用率，并大幅降低社会所有部门的计算成本。拟议的项目将为通用计算机互连开发一种与光外围组件互连Expreess(PCIe)兼容的透明网桥。PCIe是当今计算机中使用最普遍的互连。该方案中开发的技术基于基于发光二极管(LED)的发射器、多芯光纤和与互补金属氧化物半导体(CMOS)兼容的光电探测器，旨在将电气解决方案的电力消耗从~10pJ/bit降低到~100-200fJ/bit。LED的使用充分利用了在成本和电力效益高的LED照明和显示器方面已经进行的投资。LED和多芯光纤的小尺寸允许数据密度为1PBPS/cm2。电互连和其他光学互连技术无法与这些基于LED的光学互连的性能相比。这些优势实现了计算、存储和内存功能的物理分解，从而提高了系统性能和资源利用率。这一第二阶段的工作重点是为芯片到芯片和芯片到存储器互连的应用开发符合PCIe标准的透明桥。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to create very low power and very high capacity optical interconnects for general computer applications. Computer performance is limited by the speed, power, and latency of connections between chips and memory. The limitations of electrical interconnects are well known, and optical interconnects overcome the limitations and offer 100-1000 times performance improvements. While historically optical interconnects have been hampered by high cost and high power, recent developments show that the promise of optical interconnects can be practically realized. Optical interconnects will dramatically improve overall performance of enterprise and cloud computing services, especially when used in data center computers, while reducing electrical power consumption. This will in turn permit a vast improvement in resource utilization and dramatic reduction in the cost of computation across all segments of societyThe proposed project will develop an optical peripheral component interconnect expreess (PCIe)-compatible transparent bridge for general computer interconnects. PCIe is the most prevalent interconnect used today in computers. The technology developed in this proposal, based on light emitting diode (LED)-based transmitters, multicore optical fibers, and complementary metal-oxide semiconductor (CMOS)-compatible photodetectors, seeks to reduce electrical power consumption from ~10 pJ/bit for electrical solutions to ~100-200 fJ/bit. The use of LEDs leverages investments already made for cost and power effective LED lighting and displays. The small size of the LEDs and multicore fibers allows for data densities of 1 Pbps/cm2. Electrical interconnects and other optical interconnect technologies cannot compare with the performance of these LED based optical interconnects. These advantages enable physical disaggregation of the compute, storage, and memory functions, improving system performance and resource utilization. This Phase II effort is focused on the development of a PCIe-compliant transparent bridge for applications in chip to chip and chip to memory interconnects.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.