Collaborative Research: SaTC: CORE: Medium: Systematic Detection Of and Defenses Against Next-Generation Microarchitectural Attacks

很难对敏感数据进行计算，而不会无意中将其泄露给错误的一方。更糟糕的是，处理器设计大大加剧了这个问题。具体地说，处理器由性能优化(称为微体系结构)组成。研究表明，精明的攻击者可以操纵微体系结构来泄露敏感数据。该项目的创新之处在于设计了通过安全镜头分析微体系结构的方法和工具：捕捉其泄露敏感数据的可能性，并向硬件设计人员和软件编写人员提供可行的反馈，以帮助避免在硬件设计时和软件运行时发生敏感数据泄露。该项目的更广泛的影响和重要性是开发一种方法来构建高效、安全的处理器-即那些性能和安全性不是相互排斥的处理器。该项目分为两个协同推进。推力1，分析，开发了一些技术，用于理解和简洁地描述微体系结构组件(在其开发的不同阶段)在将其集成到更大的设计中时的信息泄漏潜力。推力2，强化，开发用于使用例如由推力1生成的所述表征(规范)来导出软件缓解的技术。在这两种推进中，一个主要目标是开发可以自动化的技术。相应地，到项目结束时，目标是开发和传播完整的端到端原型框架，该框架可以与传统的硬件设计流程一起使用，以1)实现硬件工程师的安全效率合作设计，以及2)保护在先前分析的微体系结构上运行的程序。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

It is difficult to compute on sensitive data without inadvertently leaking it to the wrong party. Making matters worse, processor design significantly exacerbates this problem. Specifically, processors are made up of performance optimizations (called microarchitecture). Research has shown how a savvy attacker can manipulate microarchitecture to leak sensitive data. This project’s novelties are to design methodologies and tools for analyzing microarchitecture through a security lens: capturing its potential to leak sensitive data and providing actionable feedback to hardware designers and software writers to help avoid sensitive data breaches at both hardware design time and software run time. The project’s broader impact and importance is to develop a means for building efficient, secure processors—i.e., those where performance and security are not mutually exclusive.The project is broken into two synergistic thrusts. Thrust 1, Analysis, develops techniques for understanding and succinctly characterizing the information leakage potential of microarchitectural components (at various stages in their development) when they are integrated into a larger design. Thrust 2, Hardening, develops techniques for using said characterizations (specifications), e.g., generated by thrust 1, to derive software mitigations. In both thrusts, a major goal is to develop techniques that can be automated. Correspondingly, by the end of the project, the goal is to develop and disseminate a complete end-to-end prototype framework that can be used alongside traditional hardware design flows to 1) enable security-efficiency co-design by hardware engineers and 2) protect programs when run on previously analyzed microarchitectures.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.