FMitF: Track I: A Holistic Approach Towards Online Monitoring of Integrated Circuits and Systems

芯片设计和系统集成的复杂性不断增加，对第三方硬件组件的依赖以及不可靠的全球半导体供应链为引入错误提供了可能性。这些错误可能是设计缺陷和忽略的操作条件的无意后果，也可能是故意攻击者引起的。最近，已经表明存在更具有挑战性的威胁，其中攻击者在制造之前通过对硬件设计的恶意修改来操纵硬件操作。考虑到意外错误和恶意修改硬件组件的可能性以及检测所有这些问题的难度，该项目通过在正常部署和操作期间监控装配的硬件组件来开发最后一道防线。这种方法能够检测攻击或其他违反系统完整性和安全性的情况。该项目的创新之处是开发了一种严格的方法来监测集成电路的运行，并设计了一个软件工具链和实现监测器的硬件原型。该项目的影响是在硬件的可靠性，安全性和安全性的进步，形成了计算系统的基础。该项目开发了一种新的监控规范语言，称为FlowSL，用于描述与系统的完整性和安全性相关的属性。FlowSL超越了基于时态逻辑和正则表达式的既定方法，以便在表达性和易于在硬件上高效执行之间实现平衡。原理性的编译和编译算法是为了有效地将监视器规范转换为原始的硬件操作而设计的。规范语言与可编程硬件加速器共同设计。该项目在硬件中设计了高度优化的计算原语，用于实现FlowSL的各个运算符，以及一个可扩展和可编程的流水线架构，使多个原语的组合能够实现监视器。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

The ever-increasing complexity of chip design and system integration, the reliance on third-party hardware components, and the untrustworthy global semiconductor supply chains open up the possibility for the introduction of errors. These errors can be unintentional consequences of design bugs and neglected operating conditions or induced by intentional attackers. Recently, it has been shown that even more challenging threats exist where the attackers manipulate the hardware operations via malicious modifications of a hardware design before fabrication. Given the possibility of unintentional errors and maliciously modified hardware components and the difficulty of detecting all these issues, this project develops one last line of defense by monitoring fabricated hardware components during normal deployment and operation. This approach enables the detection of attacks or other conditions that violate the system's integrity and security. The project's novelties are the development of a rigorous approach for monitoring the operation of integrated circuits and the design of a software toolchain and hardware prototype that realizes the monitors. The project's impacts are advances in the reliability, safety and security of the hardware that forms the basis of computing systems.The project develops a novel monitor specification language, called FlowSL, for describing properties that are relevant for the integrity and security of a system. FlowSL goes beyond established approaches based on temporal logic and regular expressions in order to achieve a balance between expressiveness and being amenable to efficient execution on hardware. Principled heuristics and compilation algorithms are designed for the effective translation of monitor specifications into primitive hardware operations. The specification language is co-designed with a programmable hardware accelerator. The project designs highly optimized computational primitives in hardware, which are used for realizing individual operators of FlowSL, and a scalable and programmable pipeline architecture that enables the composition of several primitives to implement the monitors. A full-stack prototype is developed, which is evaluated on representative applications from the domains of hardware security and runtime verification of cyber-physical systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.