Silicon spin qubits: Exploring an epitaxial materials platform for controllable valley splitting and charge noise mitigation

在高度集成和可扩展的半导体环境中，单电子的自旋是最有希望定义量子比特的候选者之一。通过门定义量子点在硅锗中定位的自旋最近在操作保真度和可扩展量子计算架构的想法方面取得了重大进展。在我们之前的项目中，我们自己已经展示了高富集28Si/SiGe的最先进的量子比特，最长的回波相干时间和高谷分裂。然而，人们一致认为，这些基于Si/Si的量子比特的电荷噪声、电位无序和谷分裂需要在再现性方面得到改进，以实现进一步的可扩展性。到目前为止，量子比特器件的材料物理几乎没有得到解决，尽管可以预见，它对目前观察到的极限有很大的贡献。关于电荷噪声和电位波动，我们之前的实验指出了Si/SiGe异质结构和氧化物介电介质之间的界面的特殊作用。我们在此建议用替代氧化物取代目前世界范围内使用的无定形氧化铝及其所有带电缺陷。我们的重点将放在通过分子束外延、原位外延和单晶在Si/SiGe异质结构上生长的氧化物上。这将最大限度地减少界面和电介质中的杂质和缺陷，并在我们对单个量子比特的噪声分析中得到显著反映。Si/SiGe中自旋量子位的谷分裂目前主要由局部短程原子杂质（如步骤）主导。在这里，我们想利用垂直于Si/SiGe量子阱的电场，另外，可以显著地促进谷分裂。因此，我们将通过全局后门扩展表面门控制的量子比特器件。这将使我们能够在异质结构上施加比目前研究状态下可能的更高的电场。实验上，谷分裂的显著增加是预期的，这一方面将大大促进自旋量子比特的操作，同时-由于全局后门-承诺在局部空间中分裂的波动更低。在该项目中，我们还将引入局部强局部退火，通过内部设计的激光扫描仪在量子比特组件的欧姆接触处激活植入供体，以取代目前世界范围内使用的整个组件的高温退火步骤。由此产生的Si/SiGe/介电量子比特结构中体积扩散的显著减少将导致电荷噪声和电位波动的减少以及可重复的高谷分裂。

The spin of single electrons is one of the most promising candidates to define qubits in a highly integrated and scalable semiconductor environment. Spins localized in silicon-germanium by means of gate-defined quantum dots have recently seen major advances in manipulation fidelities and ideas for scalable quantum computing architectures. In our previous project, we, ourselves, have demonstrated a state-of-the-art qubit in highly enriched 28Si/SiGe, longest echo coherence time and high valley splitting. However, there is a consensus that charge noise, potential disorder and valley splitting of these Si/SiGe-based qubits need to be improved in terms of reproducibility to implement further scalability. The material physics of the qubit devices has been scarcely addressed so far, although it is foreseeable that it contributes significantly to the currently observed limits.With respect to charge noise and potential fluctuations, our previous experiments point to the special role of the interface between the Si/SiGe heterostructure and the oxide dielectric. We propose here to replace the amorphous aluminum oxide - with all its charged defects - currently used worldwide by alternative oxides. Our focus will lie on an oxide that is grown by molecular beam epitaxy, in-situ, epitaxially and monocrystalline on the Si/SiGe heterostructure. This should minimize impurities and defects at the interface and in the dielectric and be significantly reflected in our noise analyses of single qubits. The valley splitting for spin qubits in Si/SiGe is currently dominated by local short-range atomic impurities such as steps. Here, we want to exploit that an electric field perpendicular to the Si/SiGe quantum well can, additionally, significantly contribute to the valley splitting. Therefore, we will extend our surface gate controlled qubit devices by a global backgate. This will enable us to apply considerably higher electric fields to the heterostructure than is possible in the current state of research. Experimentally, a significant increase of the valley splitting is expected, which on the one hand will considerably facilitate the manipulation of spin qubits and at the same time - due to the global backgate - promises lower fluctuations of the splitting in the local space. Within the project we will also introduce locally strongly localized annealing for the activation of implanted donors in the Ohmic contacts of the qubit components by means of an in house-designed laser scanner to replace the currently worldwide used high temperature annealing step of the entire component. The resulting significant reduction of volume diffusion in the Si/SiGe/dielectric qubit structure will result in reduced charge noise and potential fluctuations as well as in reproducibly high valley splitting.