Ensuring Robustness in Low-Power Asynchronous Circuits - ENROL

目前，几乎所有相当复杂的数字电路，如微处理器，其所有内部操作序列都由刚性时钟控制，即这些电路的操作是同步的。另一种设计范例，即异步设计，在经过适当优化后，可以实现具有更高能效、更高性能和更高健壮性的相同功能。ENROL项目致力于后一个方面，即异步设计在多大程度上确实比同步设计更健壮，就更能容忍外部干扰或次优操作条件而言。为此，在第一步中，应详细阐述根据最相关的现有异步方法设计的异步电路的无故障行为的正式模型。在下一步中，所有可能的故障影响应在该模型中表示，分类并与其各自的概率相关联。对于那些最终被容忍的错误，应该探索这种容忍的机制。由此获得的结果应与同类同步电路的结果进行比较，以证明异步电路的假设具有更高的鲁棒性；差异应通过适当的度量来量化。在这个过程中，理论考虑将伴随着全面的模拟研究和实验测量电路，其设计也是项目的一部分。在深入了解故障效应和固有容错机制的基础上，可以对异步电路和概念进行有针对性的修改和扩展，以进一步增强其鲁棒性。在这里，可用的概念范围从技术增强（晶体管几何形状和放置）到电路的变化到编码方法。虽然异步设计的容错方法已经在文献中存在，但从建模到实验的系统处理主题，涵盖所有相关的异步设计范式，并直接比较所有替代方案，显然代表了对艺术状态的贡献。ENROL的结果将为异步设计提供证据，并更好地利用异步设计的健壮性优势。这可能使后者对关键应用更具吸引力，在这些应用中，设计师也会欣赏其他优势，如能源效率或更高的性能。因此，从长远来看，ENROL将有助于构建快速节能的计算机，这些计算机在故障和次优条件下仍能可靠地工作。

Currently, virtually all reasonably complex digital circuits, such as microprocessors, have all their internal operational sequences controlled by a rigid clock, i.e. these circuits operate synchronous. An alternative design paradigm, namely asynchronous design, when suitably optimized, offers the potential for realizing the same functionality with higher energy efficiency, higher performance and higher robustness. The project ENROL is dedicated to the latter aspect, namely the question how far asynchronous designs are indeed more robust than synchronous ones, in terms of being more tolerant to external interferences or sub-optimal operating conditions. To this end, in a first step a formal model shall be elaborated for the fault-free behavior of asynchronous circuits designed following the most relevant existing asynchronous approaches. In a next step all possible fault effects shall be expressed in that model, classified and associated with their respective probabilities. For those faults that turn out to be finally tolerated, the mechanisms underlying this tolerance shall be explored. The results thus obtained shall be compared with those for comparable synchronous circuits to give evidence for the hypothesized higher robustness of asynchronous circuits; the differences shall be quantified by means of suitable metrics. In this process, theoretical considerations will be accompanied by comprehensive simulation studies and experimental measurements for circuits whose design is part of the project as well.Based on the thorough understanding of the fault effects and the inherent fault tolerance mechanisms, well directed modifications to and extensions of the asynchronous circuits and concepts can be devised to further enhance their robustness. Here, the available concepts range from technological enhancements (transistor geometry and placement) over changes in the circuit towards coding methods. While fault-tolerance approaches for asynchronous designs do exist in the literature already, the systematic treatment of the topic from modelling to experiment, covering all relevant design asynchronous design paradigms, and directly comparing all alternatives, clearly represents a contribution to the state of the art.The results of ENROL will allow to give evidence for and to better leverage the robustness benefits of asynchronous design. This could make the latter more attractive for critical applications where designers would as well appreciate the other advantages like energy efficiency or higher performance. So on the long run ENROL will contribute to constructing fast and energy-efficient computers that yet work reliable under faults and sub-optimal conditions.