Optimization of Multipliers for Reconfigurable Logic

该研究项目的目标是开发用于现场可编程门阵列（fpga）上资源和功率高效乘法器设计的算法。乘法本身属于最基本的算术运算，或者作为除法或函数近似等高阶算术的基本组成部分。尽管自20世纪50年代以来，对乘法的实现进行了研究和改进，但现场可编程门阵列作为重要实现平台的出现需要新的fpga概念，适应架构的实现对于节约资源和提高效率至关重要。应用范围从非常小的字长（例如用于神经网络）到非常大的字长（例如加密应用）。提出的工作将研究如何有效地实现从2位到数百位字长的大范围相关乘法。为此，将优化它们由较小乘数组成，以及基于逻辑的乘数和嵌入式乘数在小尺度和大尺度上的结合。此外，由于放宽精度限制，可能降低成本的潜力将基于截断和近似乘法方案进行探索。为了以共同的方式解决这些问题，应该建立一个统一的框架，该框架基于最近引入的乘数平铺思想。

The goal of this research project is the development of algorithms for the design of resource and power efficient multipliers on field-programmable gate arrays (FPGAs). Multiplications belong to the most fundamental arithmetic operations either by themselves or as basic building blocks of higher-order arithmetic like divisions or function approximations.Even though the implementation of multiplications was investigated and improved since the 1950's, the advent of field-programmable gate arrays as an important implementation platform requires new conceptsas for FPGAs an architecture-adapted implementation is imperativefor resource savings and efficiency.Applications range from very small word sizes (e.g. used in neural networks) to very large word sizes (e.g. cryptographic applications).The proposed work will investigate how the large range of relevant multiplications, ranging from 2 bits to several hundred bits word size, can be efficiently implemented.For this, their composition out of smaller multipliers as well as the combination of logic-based and embedded multipliers at a small and large scale will be optimized.Additionally, the potential of possible cost reductions due to relaxed accuracy constraints will be explored based on truncation and approximate multiplication schemes.To tackle these problems in a common way, a unified framework shall be developed which is based on a multiplier tiling idea that was introduced recently.