Theory and Design Method of Clock-less Datapath for Next Generation VLSIs

在目前和未来的超大规模集成电路纳米技术中，时钟分配不仅占用芯片面积和功耗，而且使时序问题更加严重。无时钟数据通路结构将时钟信号排除在数据通路之外，是解决时钟分配问题的一种方法。本研究的目的是展示无时钟数据通路的可能性并发展其设计方法，其中一种无时钟数据通路架构是由一个由时钟信号驱动的控制器部分和一个仅由控制器的控制信号驱动的数据通路部分组成（时钟信号不馈入数据通路部分）。另一种是由异步控制器部分和异步数据通路部分组成的控制器。本文的主要研究成果如下：1.提出了一种既考虑数据信号，又考虑分配约束的控制信号调度算法 ...更多信息 数据路径部分中的延迟和从控制器到数据路径部分中的每个组件的控制信号延迟。该调度器已被纳入一个新的综合框架称为“以分配为中心的高级综合”，形成一个完整的综合系统。2.控制信号的到达时间的差异被称为“时间偏斜”，它有可能提高数据路径的速度。我们制定了几个偏斜优化问题，3.提出了一种以分配为中心的异步数据通路高级综合方法。与传统方法相比，该方法的主要优点在于：（1）优化效率高;（2）性能统计分析。4.为了提高无时钟异步数据通路的硬件利用率，提出了一种异步寄存器的新实现。综合系统已被修改，以满足新的寄存器提供的新的寄存器共享模型。我们已经通过综合实验验证了新寄存器的有效性。少

In the current and future nanometer-technologies for VLSIs, clock distribution is chip-area consuming and power consuming, and also it makes the timing problem more serious. The clock-less data-path architecture, which excludes clock signal from the data-path part, would be one of the solutions for those problems relevant to clock distribution. The purpose of this research is to show the possibility and to develop design methodologies of the clock-less data-path. One clock-less data-path architecture considered in our study is the one which consists of a controller part driven by a clock signal and a data-path part driven by only control signals from the controller (a clock signal is not fed to the data-path part). The other is the one which consists of an asynchronous controller part and an asynchronous data-path part. The results obtained in this research are summarized as follows.1.We have proposed the assignment constraint control signal scheduling considering both the data signal … More delay in the data-path part and control signal delay from the controller to each component in the data-path part. The scheduler has been incorporated into a new synthesis framework called "assignment-centric high-level synthesis" to form a complete synthesis system.2.The difference of arrival timing of control signals is called "timing skew", and it has the potential to improve the speed of the data-path. We have formulated several skew optimization problems, studied there properties and developed optimization algorithms.3.We have proposed an assignment-centric approach to the high-level synthesis for asynchronous data-paths. The major advantages of our method over conventional ones are (1) the efficiency in optimization and (2) statistical performance analysis.4.To improve hardware utilization in the clock-less asynchronous data-path, a novel implementation of asynchronous register has been proposed. The synthesis system has been modified to meet a new register sharing model provided by the new register. We have verified the effectiveness of the new register through synthesis experiments. Less