Ultra High Speed and Intelligent Digital Signal Processing

本研究在ASIC和FPGA上实现了进化数字滤波器（edf）的并行处理，并对其性能进行了评估。EDF是一种基于生物进化策略的自适应算法控制的自适应数字滤波器（ADF）。自适应优化算法是一种基于种群的鲁棒优化方法，特别适用于解决高维、多模态的搜索空间问题。它是一种非梯度多点搜索算法。因此，它不容易受到多峰曲面产生的局部最小问题的影响。EDF可根据应用采用各种误差函数作为适应度函数，如p次范数误差函数、最大误差函数等。该自适应算法具有自稳定特性，即不稳定极点有向稳定区域迁移的趋势。此外，EDF还可以搜索靠近单位圆的极点。由于EDF具有多个内滤波器，因此并行实现可以减少计算时间。在该方法中，将复制算法改为硬件实现的简化算法。硬件EDF由滤波与适应度计算（FFC）模块和再现与选择（RS）模块组成。FFC模块有可以并行运行的子模块，因为EDF有多个内部滤波器。RS模块的子模块既可以进行无性繁殖和选择，也可以进行有性繁殖和选择。ASIC实现结果表明，EDF模块的时钟频率为20.0MHz，包含63,652个门。

This research implements evolutionary digital filters (EDFs) on the ASIC and the FPGA for its parallel processing, and evaluates its performance. The EDF is an adaptive digital filter (ADF) which is controlled by adaptive algorithm based on the evolutionary strategies of living things. The advantages of the EDF are summarized as followsThe adaptive algorithm of the EDF is a population-based and robust optimization method, especially used to tackle high-dimensional and multi-modal search space problems. It is a non-gradient and multi-point search algorithm. Thus, it is not susceptible to local minimum problems that arise from a multiple-peak surface.The EDF can adopt the various error functions as the fitness function according to application, for example, the p-power norm error function, the maximum error function and so on.The adaptive algorithm of the EDF has a self-stabilizing feature whereby unstable poles have a tendency to migrate back into the stable region. In addition, the EDF can search the poles which are near the unit circle.Since the EDF has multiple inner filters, the parallel realization can reduce the calculation time. In the proposed method, a reproduction algorithm is changed to a simplified algorithm for the hardware implementation. The hardware EDF consists of the Filtering and Fitness Calculation (FFC) module and the Reproduction and Selection (RS) module. The FFC module has the submodule that can operate parallel because the EDF has multiple inner filters. The RS module has the submodule that can perform both asexual reproduction and selection, and sexual reproduction and selection. ASIC implementation results show that the EDF module can be clocked at 20.0MHz, and it contains 63,652 gates.