Self-Timed High-Performance Real-time Processing Architecture

本研究计画的目标是建立一个基于完全自定时管线架构的高效能网路处理器架构。在项目实施过程中取得了以下研究成果。下一代高速网络处理器需要实现高速分组转发，引入新的协议和高功能的网络服务，并且沿着有效的处理速率来节省电力。自定时超流水线数据驱动体系结构是满足这些要求的最有前途的体系结构之一，因为它能够通过在灵活的流水线硬件上可执行的超并行处理软件来实现高功能和复杂的任务。（a）高速分组分类方案分组分类是高速互联网路由器中的繁重任务之一。我们提出了一个超流水线的数据包分类方案。通过使用该方案，我们可以分类约12 M包/秒，即使在大规模的互联网交换节点有超过100 k的分类规则。（B）适用于区分服务的基于优先级的流水线方案自定时流水线方案能够凭借其局部控制在硅上实现高功能性。我们提出了一个基于优先级的调度方案，作为自定时流水线方案的一个高功能应用。一个0.18 μ m的CMOS原型芯片采用折叠自定时流水线结构，能够排队和调度100 M包/秒自主。

The objective of this research project is to establish a high-performance network processor architecture based on the fully self-timed pipeline scheme. The following research results are obtained during the project. Next-generation high-speed network processors are required to achieve high-speed packet forwarding, to introduce new protocols and highly functional network services, and also to save electric power along with effective processing rate. The self-timed superpipelined data-driven architecture is one of the most promising architectures to satisfy these requirements because it is able to realize highly-functional and complex tasks by ultra-parallel processing software executable on flexible pipelined hardware.(a)High-speed packet classification scheme Packet classification is one of heavy tasks in high-speed internet routers. We proposed a super-pipelined packet classification scheme. By using this scheme, we can classify about 12 M packets/second even in large scale internet exchange nodes having over 100 k classification rules.(b)Priority based queueing scheme applicable to Diffserv The self-timed pipeline scheme is capable to realize high functionalities on silicon by virtue of its localized control. We proposed a priority-based queueing scheme as a highly-functional application of the self-timed pipeline scheme. A 0.18 um CMOS prototype chip of the proposed scheme using a folded self-timed pipeline structure was capable to queue and schedule 100 M packets/second autonomously.