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Data-Driven Ultra-Parallel Processing Scheme Based on "Flow-Thru Processing" Concept

Data-Driven Ultra-Parallel Processing Scheme Based on "Flow-Thru Processing" Concept
基于“Flow-Thru处理”概念的数据驱动超并行处理方案
批准号:
63850067
负责人:
TERADA Hiroaki
金额:
$4.74万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research (B).
财政年份:
1988
资助国家:
日本
项目状态:
已结题
起止时间:
1988 至 1990

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中文摘要
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英文摘要
This research was initiated to realize the ultra parallel processing scheme on a VLSI chip by introducing the "flow-thru processing" concept. In order to establish a basis for highly parallel algorithms, we have undertaken such examples as the prime number generation (Sieve of Eratosthenes) in which high parallelisms existent in the target problem must execute without any side effects. We have shown that the elastic pipeline based upon the "flow-thru processing" concept is effective in exploiting such parallelisms (reference no. 1). Next, a single board data-driven processor system also based upon the "flow-thru processing" concept was realized and has served as a powerful experimental system. Using the system's monitoring facilities, we have confirmed the targeted performance of 20 MOPS (reference no. 3). Performance evaluations of 40 MFLOPS were exhibited for the system's ALU, the floating point processor (reference no. 4). Evaluations also confirmed 50 mega associations per second f … More or the firing control function (reference no. 5). Encouraged from these results, a prototype of the one chip data-driven processor was fabricated as an evaluation chip which yielded performance of 50 MFLOPS (reference no. 6).Focusing upon the field programmability of programmable logic arrays, we have also began preliminary examination on variable structure elastic pipelines in order to realize a processor with more flexible capabilities.When interconnected, such a powerful single processor can also serve as processing elements in large scale multiprocessor system which promises to achieve breakthroughs in performance thus far unsuccessful with conventional processors. An antonomous distributed parallel associative processor coined the catalytic ring has been proposed in which two elastic pipelines flow in opposite directions while at the same time interacting with each other. We have currently began evaluations on autonomous distributed associative processing which is expected to play a fundamental role in our research toward highly parallel processing methodology to realize the next generation of knowledge processing. Less
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Komori,S.: "A 40MFLOPS 32-bit floating-point processor with elastic pipeline scheme" IEEE Journal of Solid-State Circuits. 24-5. 1341-1347 (1989)
Komori,S.:“具有弹性管道方案的 40MFLOPS 32 位浮点处理器”IEEE 固态电路杂志。
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寺田 浩詔: "VLSI向きデ-タ駆動プロセッサ:Qーx" 電子情報通信学会論文誌(D). 8. 1383-1390 (1988)
Hiroyuki Terada:“VLSI 的数据驱动处理器:Q-x”《电子、信息和通信工程师学会汇刊》(D) 8. 1383-1390 (1988)。
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43
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