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Data-Driven Ultra-Parallel Processing Scheme Based on "Flow-Thru Processing" Concept

基于“Flow-Thru处理”概念的数据驱动超并行处理方案

基本信息

批准号：
63850067
负责人：
TERADA Hiroaki
金额：
$ 4.74万
依托单位：
Osaka University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research (B).
财政年份：
1988
资助国家：
日本
起止时间：
1988 至 1990
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-63850067/
关键词：
Ultra Parallel Algorithm VLSI Ultra Parallel Processing Scheme Data-driven Diagrammatical Language Flow-thru Processing Programmable Logic Array Multiple Valued Logic データ駆動

项目摘要

This research was initiated to realize the ultra parallel processing scheme on a VLSI chip by introducing the "flow-thru processing" concept. In order to establish a basis for highly parallel algorithms, we have undertaken such examples as the prime number generation (Sieve of Eratosthenes) in which high parallelisms existent in the target problem must execute without any side effects. We have shown that the elastic pipeline based upon the "flow-thru processing" concept is effective in exploiting such parallelisms (reference no. 1). Next, a single board data-driven processor system also based upon the "flow-thru processing" concept was realized and has served as a powerful experimental system. Using the system's monitoring facilities, we have confirmed the targeted performance of 20 MOPS (reference no. 3). Performance evaluations of 40 MFLOPS were exhibited for the system's ALU, the floating point processor (reference no. 4). Evaluations also confirmed 50 mega associations per second f … More or the firing control function (reference no. 5). Encouraged from these results, a prototype of the one chip data-driven processor was fabricated as an evaluation chip which yielded performance of 50 MFLOPS (reference no. 6).Focusing upon the field programmability of programmable logic arrays, we have also began preliminary examination on variable structure elastic pipelines in order to realize a processor with more flexible capabilities.When interconnected, such a powerful single processor can also serve as processing elements in large scale multiprocessor system which promises to achieve breakthroughs in performance thus far unsuccessful with conventional processors. An antonomous distributed parallel associative processor coined the catalytic ring has been proposed in which two elastic pipelines flow in opposite directions while at the same time interacting with each other. We have currently began evaluations on autonomous distributed associative processing which is expected to play a fundamental role in our research toward highly parallel processing methodology to realize the next generation of knowledge processing. Less

本研究借由引入“流通式处理”的概念，在超大型积体电路晶片上实现超平行处理。为了建立一个高度并行算法的基础，我们已经进行了这样的例子作为素数生成（筛的Eratosthenes），其中存在于目标问题中的高并行性必须执行没有任何副作用。我们已经表明，基于“流通处理”概念的弹性管道在利用这种并行性方面是有效的（参考文献1）。其次，一个单板数据驱动的处理器系统，也基于“流通处理”的概念，实现了，并已作为一个强大的实验系统。利用该系统的监测设施，我们已经确认了20个MOPS的目标性能（参考编号3）。40 MFLOPS的性能评估展示了系统的ALU，浮点处理器（参考编号4）。评估还证实了每秒50个百万关联f ...更多信息或点火控制功能（参考号5）。受这些结果的鼓舞，制造了单芯片数据驱动处理器的原型作为评估芯片，其产生50 MFLOPS的性能（参考文献6）.集中于可编程逻辑阵列的现场可编程性，我们也已经开始对可变结构弹性流水线进行初步检查，以便实现具有更灵活能力的处理器。当互连时，这种强大的单个处理器也可以用作大规模多处理器系统中的处理元件，该大规模多处理器系统有望实现迄今为止在传统处理器中不成功的性能突破。本文提出了一种称为催化环的自适应分布并行联想处理机，其中两条弹性管道反向流动，同时又相互作用。我们目前已经开始评估自主分布式联想处理，预计将发挥基础作用，在我们的研究高度并行处理方法，实现下一代的知识处理。少