Ultra-wideband highly linear Sampler and Analog-to-Digital Converter – DISCO

该研究计划解决了采样率为128 GS/s及以上的超高速宽带模数转换器（ADC）架构领域，目标奈奎斯特信号带宽至少为60 GHz，同时保持有效比特数（ENOB）超过6，从而使下一代光纤、雷达和无线通信系统的数据速率超过200 GBit/s每波长。为了解决这些具有挑战性的性能指标，研究了一种时间交错输入缓冲感应峰值跟踪保持（T/H）拓扑，该拓扑应用了一种新的有源块调制技术。该架构利用现代完全耗尽绝缘体上硅（FDSOI）技术增强的后门功能来实现有源负反馈体调制方案，从而显着提高可获得的带宽，同时改善前端线性度。与最先进的CMOS和SiGe BiCMOS方法相比，这实现了单片集成，显著降低了功耗问题。对于以下ADC核心，提出了闪存和连续近似寄存器（SAR） ADC的组合，从而结合了两者的优点，即在闪存ADC的单个时钟周期内转换多个比特和SAR ADC的本地功率和面积效率，在两步子ADC通道中。此外，提出的SAR-ADC利用先进的环展开拓扑来实现超快的转换时间。此外，现有的带宽限制以及时间交错采样相位不匹配进行了分析、建模和校准，使用混合信号方法，即基于功率高效数字相关的带宽和相位误差估计，同时使用创新的模拟校正与亚飞法拉电容调谐实现几十飞秒范围内的相移。成功地结合这些创新将为信噪比（SNR），无杂散动态范围（SFDR），采样率和信号带宽方面的显着性能改进打开大门，同时与当前最先进的技术相比，提高了功率效率，从而产生了突出的科技成果潜力。

This research proposal addresses the field of ultra-high-speed, wideband analog-to-digital converter (ADC) architectures with sample rates of 128 GS/s and beyond with target Nyquist signal bandwidth of at least 60 GHz while maintaining an effective number of bits (ENOB) of more than 6 to enable the next generation of fiber optics, radar and wireless communication systems with data rates of beyond 200 GBit/s per wavelength. To address these challenging performance metrics, a time-interleaved input-buffered inductively peaked track-and-hold (T/H) topology is investigated which applies a novel active bulk modulation technique. The architecture makes use of the enhanced back-gate capabilities of modern fully depleted silicon-on-insulator (FDSOI) technologies to implement an active negative-feedback bulk modulation scheme, thereby significantly enhancing the obtainable bandwidth while improving the front-end linearity at the same time. This enables monolithic integration and significantly reduced power concerns compared to state-of-the-art CMOS and SiGe BiCMOS approaches.For the following ADC core, a combination of Flash- and successive-approximation-register (SAR)-ADC is proposed, thereby combining the benefits of both, namely the conversion of multiple bits in a single clock cycle of the Flash-ADC and the SAR ADCs native power and area efficiency, in a two-step sub-ADC lane. Furthermore, the proposed SAR-ADC takes advantage of an advanced loop-unrolled topology to achieve ultra-fast conversion times. In addition, existing bandwidth limitations as well as time-interleaved sample phase mismatches are analyzed, modelled and calibrated using a mixed-signal approach, i. e. power-efficient digital correlation-based estimation of the bandwidth- and phase-errors while using an innovative analog correction with sub-femtofarad capacitor-tuning achieving phase shifts in the range of tens of femtoseconds.Successfully combining these innovations will open the door for significant performance improvements in terms of signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), sample rate and signal bandwidth while at the same time improving the power efficiency compared to the current state-of-the-art, yielding outstanding potential for scientific and technological achievements.