Fully Integrated Optoelectronic Receiver with Robust PAM-N Data Recovery (FIORD)

最先进的硅光子收发器在发射器和接收器侧都使用信号处理，主要使用片外数字信号处理器（DSP）执行。这些解决方案受到高达64 Gbaud的通信速度的影响，因为这些速度受到诸如键合线等互连技术的严重限制。下一代光电子系统要求每单波长和通道至少2- 4倍更高的数据速率，使得这种互连成为光电子收发器朝向1-Tbps的基本瓶颈。所提出的实现这种传输速率的架构解决方案的第一个关键创新是采用完全单片实现，其中光学组件和电子Rx和Tx电路，包括关键时钟和数据恢复（CDR）以及所需的第一级数字信号处理单元，都嵌入在同一硅衬底上。单片集成的时钟和数据恢复（CDR）以及低相位噪声PLL的其他架构创新确保了对输入PAM-N数据集的宽带动态相位和频率跟踪，对于提供等于或超过每个波长和通道224 Gbit/s的每个载波数据速率至关重要。因此，建议集中在各种PAM-N，（N=4，6，8）调制方案，以实现这一目标。显然，最佳架构选择会导致噪声（SNR）、CDR跟踪带宽和抖动、PAM-N线性度（RLM）和信号带宽之间的权衡分析。为了保证稳健的PAM-4 / PAM-6 / PAM-8 CDR操作具有上级误码率（BER）和改进的每个传输比特的能量效率，将解决以下科学和技术挑战：新的锁相算法适用于高速PAM-4 / PAM-6 / PAM-8信号，消除数据相关抖动2.超低相位噪声CDR和PLL 3.具有足够均衡的高灵敏度宽带TIA 4.高线性宽带T& H和精确ADC 5.通常用于NRZ数据的传统相位检测器（PD）（例如，亚历山大PD（APD））在应用于PAM-N信号时导致不可接受量的数据相关抖动，这是由具有不同相位延迟的中间信号转变引起的。该提案引入了一种新颖的CDR方法，特别是针对PAM-N信号定制的，并且克服了所提到的问题。该研究提案的最终目标是通过展示用于未来光子收发器的单片集成高速低抖动PAM-N CDR解决方案，推进最先进的光Rx架构。该技术不仅能够显著提高鲁棒性和误码率，而且更重要的是能够显著提升数据速率。

State-of-the-art silicon photonic transceivers use signal processing at both transmitter and receiver sides mostly performed using off-chip digital signal processors (DSPs). These solutions suffer from communication speeds up to 64 Gbaud, as these are severely limited by interconnect technologies such as bond wires. Next generation opto-electronic systems require at least 2-4x higher data rates per singe wavelength and lane, making such interconnect a fundamental bottleneck for opto-electronic transceivers towards 1-Tbps.The first key innovation of the proposed architectural solution to enable such transmission rates is the adoption of a fully monolithic implementation, where both optical components and electronic Rx and Tx circuits, including the critical clock and data recovery (CDR) together with the required first level digital signal processing units, are embedded on the same silicon substrate. Additional architectural innovations of the monolithically integrated clock and data recovery (CDR) together with a low-phase noise PLL, ensures wideband dynamic phase and frequency tracking of the incoming PAM-N data sets, is of fundamental importance to provide data rates per carrier equal or beyond 224 Gbit/s per wavelength and lane. Thus proposal focuses on various PAM-N, (N=4, 6, 8) modulation schemes to achieve this goal. Obviously, the optimum architectural choice results in a trade-off analysis between noise (SNR), CDR tracking bandwidth and jitter, PAM-N linearity (RLM) and signal bandwidth. In order to guarantee a robust PAM-4 / PAM-6 / PAM-8 CDR operation with superior bit-error rate (BER) and improved energy-efficiency per transmitted bit, the following scientific and technical challenges will be addressed: 1. New phase-locking algorithms suited for high-speed PAM-4 / PAM-6 / PAM-8 signals, eliminating the data dependent jitter 2. Ultra-low phase noise CDR and PLL 3. High-sensitivity wideband TIAs with adequate equalization 4. Highly linear wideband T&Hs and accurate ADCs 5. Traditional phase detectors (PD) such as the Alexander PD (APD), commonly used for NRZ data, lead to an unacceptable amount of data dependent jitter when applied to PAM-N signals, caused by the intermediate signal transitions with different phase delays. This proposal introduces a novel CDR approach, particularly tailored for PAM-N signals and overcoming the mentioned issues. The ultimate objective of this research proposal is to advance state-of-the-art optical Rx architectures by demonstrating a monolithically integrated high-speed low-jitter PAM-N CDR solution for future photonic transceivers. This technology not only enables significant robustness and bit-error rate improvements, but more importantly enables significant data rate up-scaling.