Digital High-Linear Closed-Loop CMOS Transmitter with Highest Energy Efficiency for Future Mobile Radio Generations (DigiMOST)

这项应用旨在实现一种新型的数字发射机，用于具有高信号带宽的节能手机，以满足未来几代移动通信的需要。该项目提出了一种纯数字发射机的概念，将功率放大器集成到反馈环路中。因此，放大器不可避免的非线性会在出现时得到修正，从而消除了对耗时的表征的需要。反馈回路加强了整个系统从输入到输出的线性度。这也意味着，与以前的发射机解决方案相反，不需要信号预失真或DPD。消除了用于预失真的有时较高的计算工作量。这为提高效率提供了自由度，可以在灵活的调制器的帮助下加以利用。第一次，这种方法可以同时最小化数字发射机的线性度和能效。这将使用一种基于CMOS的数字发射器进行演示，该发射器适用于高达6 GHz、信号带宽为500 MHz的手机。以下两个方面在这方面尤其是新的：1.在调制器反馈环路中包括数字RF功率放大器。这在模拟放大器概念中是不可能实现的，但可以在预期的项目中使用带有数字功率放大器的纯数字技术来实现。它允许即使是极端非线性的放大器或放大器的本征线性化，而无需额外的恒定参数估计或DPD2。因此，可以将放大器设计为最大能效，从而实现新的节电电路拓扑。此外，与前人的工作相比，最优调制器和闭环方法的结合为ACLR和EVM创造了足够的范围，甚至对于未来移动无线电生成的宽带信号也是如此。此外，本领域的现状还在其他方面进行了扩展：1.研究了适用于定点运算的数字功放的调制方案。将发送链的所有组件集成在单片芯片上，该单片芯片被视为黑盒，可以取代模拟发送链作为插入式替换，对于要放大的信号完全透明。使用传输频率为350-400 GHz的纳米级CMOS技术(例如22 nm FDX)，可以实现载波频率和信号带宽为5/6G的数字功率放大器。

This application aims at the realization of a novel digital transmitter for energy-efficient handsets with high signal bandwidth, as required in future generations of mobile communications. The project proposes a purely digital transmitter concept that integrates the power amplifier into a feedback loop. The inevitable nonlinearities of the amplifier are thus corrected as they arise, eliminating the need for time-consuming characterization. The feedback loop enforces the linearity of the overall system from input to output. This also means that, contrary to previous transmitter solutions, no signal pre-distortion or DPD is required. The sometimes high computational effort for pre-distortion is eliminated. This opens up degrees of freedom for improving efficiency, which can be exploited with the aid of a flexible modulator. For the first time, this approach can simultaneously minimize linearity and energy efficiency for a digital transmitter. This will be demonstrated using a CMOS-based digital transmitter for handsets up to 6 GHz with 500 MHz signal bandwidth. The following two aspects in particular are new with this: 1. Inclusion of the digital RF power amplifier in the modulator feedback loop. This is not possible with analog amplifier concepts, but can be implemented in the intended project using purely digital technology with a digital power amplifier. It allows intrinsic linearization of even extremely nonlinear amplifiers or amplifiers without additional effort for constant parameter estimation or DPD.2. Thus, the amplifier can be designed for maximum energy efficiency, enabling new and power-saving circuit topologies. In addition, in contrast to all previous work, the combination of optimal modulator and closed-loop approach creates sufficient scope with regard to ACLR and EVM even for broadband signals of future mobile radio generations.In addition, the state of the art is extended in other respects as well:1. Investigation of the proposed modulation scheme for a digital PA for suitability for fixed-point arithmetic.2. Integration of all components of the transmit chain on a monolithic chip which, viewed as a black box, can replace analog transmit chains as drop-in replacement completely transparent with respect to the signal to be amplified.3. The use of a nanometer CMOS technology (e.g. 22nm FDX) with transit frequencies of 350-400GHz enables the realization of digital power amplifiers with 5/6G relevant carrier frequencies and signal bandwidths.