Compiler-Directed Code Tiling for Higher Program Performance and Predictability on Multi-Level Memory Hierarchies

编程语言总是给人一种内存是扁平的感觉，而实际的计算机正在越来越多地配备深层内存层次结构，以克服处理器和内存之间不断扩大的性能差距。这种不匹配可能导致引用局部性较低和性能较差。该项目将开发一种新的阵列布局转换，称为数据平铺，与循环平铺一起使用，以显著提高多级内存层次上以阵列为主的应用程序的性能(和可预测性)。我们将探索这种联合重构，以获得整个程序、内核库、迭代模板代码和嵌入式应用程序的更高性能和可预测性。

Programming languages invariably induce a perception of memory as being flat, whereas actual computers are being equipped increasingly with deep memory hierarchies to overcome the ever-widening performance gap between processors and memories. This mismatch can result in low locality of reference and poor performance. This project will develop a new array layout transformation, called data tiling, used in tandem with loop tiling to achieve significantly improved performance gains (and predictability) for array-dominated applications on multi-level memory hierarchies. We will explore this joint restructuring to obtain higher performance and predictability for whole programs, kernel libraries, iterative stencil codes and embedded applications.