Design Space Exploration for Mixed-Criticality Systems on Adaptive MPSoC Platforms

混合关键系统（MCS）在汽车、航空电子或医疗系统等众多领域中越来越重要，并且具有更高复杂性的明显趋势。因此，系统实现正在从单核平台发展到现代异构多核架构。特别令人感兴趣的是自适应MPSoC，它允许任务不仅在CPU，GPU，AI处理单元等异构可编程单元上实现，而且还可以作为此类系统的FPGA部分中的专用硬件单元实现。这些实现方案为设计人员提供了额外的选择，以满足MCS的要求。然而，目前的设计方法不足以处理这些硬件平台提供的巨大的设计空间。该项目旨在为异构和自适应MPSoC上的MCS开发系统的设计空间探索方法和指南。主要的科学成果将是更深入地了解有关硬件平台的设计决策和任务的实施如何影响整个系统符合混合关键性要求。我们将为科学界提供三个具体的贡献：（1）我们提供了一套全面的模型，以在设计过程中早期估计MCS的相关指标。特别是，我们的计算和通信设计决策之间的相互依赖关系模型，并考虑硬件设计决策的最坏情况下的执行时间的任务的概念的基础上的时序组合的影响。(2)我们创建的算法和设计准则，利用自适应MPSoC的MCS。我们提供了不同的实施方案，关键模式，以及不同的功能模式的任务映射和通信映射策略。(3)我们开发了一种统一的方法来共同优化硬件加速器，通信基础设施和任务映射到异构处理单元的MCS。优化算法将根据在自适应MPSoC上实现的MCS的要求进行定制，以便明确考虑最坏情况下的执行时间和关键性要求。有了这些贡献，我们希望为MCS的自适应MPSoC的广泛使用奠定坚实的基础，使设计人员能够执行完整的系统优化，尽管初始设计空间的巨大规模。

Mixed-criticality systems (MCS) are of increasing importance in numerous fields, like automotive, avionics, or medical systems, with a clear trend towards higher complexity. As a result, system implementations are evolving from single-core platforms to modern heterogeneous multi-core architectures. Of particular interest are adaptive MPSoCs, which allow tasks to be implemented not only on heterogeneous programmable units such as CPUs, GPUs, AI processing units but also as dedicated hardware units in the FPGA part of such systems. These implementation alternatives give designers additional options to fulfill the requirements of MCSs. However, current design methodologies are insufficient to deal with the enormous design space offered by these hardware platforms. This project aims to develop systematic design space exploration heuristics and guidelines for MCSs on heterogeneous and adaptive MPSoCs. The main scientific outcome will be a deeper understanding of how design decisions regarding the hardware platform and the implementation of the tasks affect the overall system’s compliance with mixed-criticality requirements. We will provide three specific contributions to the scientific community: (1) We provide a comprehensive set of models to estimate the relevant metrics of MCSs earlier in the design process. In particular, we model interdependencies between computation and communication design decisions and consider the effects of hardware design decisions on the worst-case execution time of tasks based on the concept of timing compositionality. (2) We create algorithms and design guidelines for the utilization of adaptive MPSoCs in MCSs. We provide task mapping and communication mapping strategies for different implementation alternatives, criticality modes as well as different functional modes. (3) We develop a unified approach to co-optimize hardware accelerators, communication infrastructure and the mapping of tasks onto heterogeneous processing units in MCSs. The optimization heuristics will be tailored to the requirements of MCSs implemented on adaptive MPSoCs, so that worst-case execution time and criticality requirements are explicitly considered. With these contributions, we expect to lay a strong foundation for widespread use of adaptive MPSoCs for MCSs, enabling the designers to perform a complete system optimization, despite the vast size of the initial design space.