Technology-aware 3D interconnect architectures for heterogeneous SoCs manufactured in monolithic 3D integration

单片3D集成(M3D)是一种用于3D系统芯片设计的颠覆性技术。与更传统的3D集成方案相比，M3D允许相邻层之间的垂直互连的非常密集的集成。再加上外部异质性，即具有不同电气特性的层的组合，出现了新的架构设计和扩展的系统功能的前所未有的机会。这些好处已经被大量涉及处理元件和存储器的工作所证明；然而，对于诸如片上网络之类的片上通信体系结构，相关的工作却很少。此外，这些工作往往忽略了单片制造引起的本征异构性的显著影响，例如较高层上与工艺相关的晶体管退化、较低层上的互连退化，或者布线资源在层之间的不均匀分布。最后，以前的工作主要是利用3D中的线长缩减，而没有考虑扩展的微观和宏观建筑设计空间。我们希望通过分析单片3D集成的特征如何影响单个网络组件的微体系结构的设计以及通信基础设施的体系结构来解决所有这些缺点。此外，我们还将分析这些修改和扩展设计选项对整体系统架构的影响。该项目将为科学界提供四个具体的贡献：1)它将为优化的3D互连体系结构提供系统的设计指南和一套体系结构模板，以解决外部和内在的异构性；2)它将提供作为优化问题的芯片上网络拓扑综合的模型；3)它将提供一个工具集，用于支持系统的设计空间探索，这将考虑到所有相关的M3D技术特征；4)该项目将通过一个片上视觉系统和一个多处理器系统两个演示来展示优化潜力。该项目的主要成果将是更深入地理解如何利用单片3D集成的破坏性特征来改进3D集成电路中的互连结构。这允许设计优化的系统，而当前的设计概念不支持这一点。

Monolithic 3D integration (M3D) is a disruptive technology for the design of 3D System-on-Chips. In contrast to more conventional 3D integration schemes, M3D permits a very dense integration of vertical interconnects between neighboring tiers. Together with extrinsic heterogeneity, i.e., the combination of tiers with different electrical characteristics, unprecedented opportunities for new architectural designs and extended system functionalities arise. These benefits have been proven by numerous works addressing processing elements and memories; yet, for on-chip communication architectures such as Network-on-Chips, only few related works exist. Further on, these works often neglect the significant impact of intrinsic heterogeneity caused by monolithic fabrication, such as process-related transistor degradations on higher tiers, interconnect degradations on lower tiers, or the non-uniform distribution of routing resources among tiers. Finally, previous works primarily exploit wire length reduction in 3D, yet do not consider the extended micro- and macroarchitectural design space. We want to address all of these shortcomings by analyzing how the characteristics of monolithic 3D integration affect the design of the microarchitecture of individual network components, and the architecture of the communication infrastructure. Furthermore, we will analyze the impact of these modifications and extended design options on the overall system architecture. The project will provide four specific contributions to the scientific community: 1) It will provide systematic design guidelines and a set of architectural templates for optimized 3D interconnect architectures addressing extrinsic and intrinsic heterogeneity; 2) It will provide models for formulating Network-on-Chip topology synthesis as an optimization problem; 3) It will provide a toolset for supporting a systematic design space exploration, which accounts for all relevant M3D technology characteristics;4) It will demonstrate the optimization potential by means of two demonstrators, a Vision-System-on-Chip and a multiprocessor system.The main outcome of this project will be a deeper understanding on how the disruptive characteristics of Monolithic 3D integration can be exploited for improving the interconnect architecture in 3D integrated circuits. This allows for the design of optimized systems, not supported by current design concepts.