Research on Reconfigurable General Purpose Co-processor Systems and Their Optimized Hardware/Software Codesign Compiler

我们研究了具有可重构通用协处理器的计算机系统，以及这些系统的硬件/软件协同设计环境。我们的研究结果如下：1。我们提出了一种由fpga（现场可编程门阵列）、缓存存储器和总线接口组成的可重构协处理器架构。我们已经为Sun工作站设计并实现了一个协处理器的原型。协处理器包括4个fpga，一个1mb缓存存储器和一个带有硬件队列的总线接口。提出了一种基于协处理器的计算机系统软硬件协同设计环境。研究了系统描述语言和主处理器与协处理器之间的协作方法。我们用C语言程序设计并实现了协处理器系统的协同设计环境。硬件/软件协同设计编译器接受一个C程序，并估计每个函数的执行时间和硬件成本……当函数作为硬件实现时更多。编译器还通过软件实现估算函数的执行时间。然后由编译器决定每个函数的实现方法。研究了在fpga上作为硬件模块实现的C程序的优化方法。我们介绍了与硬件无关的优化方法，如循环展开、可变位长缩减、函数扩展等。优化方法，如基于4-1 LUT（查找表）的硬件估计方法、位级操作的边际法等。我们在协同设计系统的原型上测试了几种算法，其中包括词法分析、排序和几个图形应用程序。我们发现，当程序包含并行if结构或位级操作时，基于FPGA的协处理器对于程序的快速执行是有用的。在未来，我们想研究上下文切换在协处理器系统，和协处理器的动态可重构性。少

We have investigated computer systems with reconfigurable general purpose co-processors, and the hardware/software codesign environment for the systems. The results of our research are as follows :1. We have proposed a reconfigurable coprocessor architecture made of FPGAs (Field Programmable Gate Arrays), a cache memory, and a bus interface.2. We have designed and implemented a prototype of the co-processor for Sun workstations. The coprocessor includes 4 FPGAs, a 1 MB cache memory, and a bus interface with a hardware queue.3. We proposed a hardware/software codesign environment for the computer system with the co-processor. We have investigated the system description languages and the co-operation method between the main processor and the co-processor.4. We have designed and implemented the codesign environment from C programs for the coprocessor system. The hardware/software codesign compiler accepts a C program and estimates the execution time and the hardware costs of each function … More when the function is implemented as a hardware. The compiler also estimates the execution time of the function with the software implementation. Then the compiler decides the implementation method of each function.5. We have investigated the optimization method of C programs to be implemented as hardware modules on FPGAs. We have introduced hardware independent optimization methods such as the loop-unrolling, the variable bit-length reduction, the function expansion, ets., optimization methods such as the 4-1 LUT (Look-Up Table) based hardware estimation method, the marge method of bit-level operations, etc.6. We have tested several algorithms on the prototype of the codesign system, which include lexical analysis, sorting, and several graphic applications. We have found that the FPGA based co-processor is useful for the fast execution of programs, when the program include the parallel-if structure or the bit-level operations.In the future, we would like to investigate context switching on the co-preoessor system, and dynamic reconfigurability of the co-processor. Less