The Via-Programmable LSI Design Architecture using EB direct writing and it's application to Unique LSI for the Authentication device.

由于超大规模集成电路微制造技术的进步，由微处理器和大容量存储器组成的集成电子系统可以作为一块芯片实现。基于标准单元的ASIC的光掩模成本已经增加到令人望而却步的地步，由于包括掩模成本在内的高非重复工程(NRE)成本，小批量生产的LSI很难制造。电子束直写(EBDW)技术是最具成本效益的光刻工具，因为它是无掩模技术。采用字符投影(CP)电子束直写将大大缩短电子束曝光时间。为此，我们开发了适合于这种CPEB直写的LSI器件结构。2006年，我们提出了一种用户可编程的VPEx(Via Programable Logic Device Using异或阵列)结构，该结构可以通过改变2个通孔上的版图来对硬件逻辑进行编程。VPEx的逻辑元件(LE)由复门型异或(EXOR)和反相器(NOT)门组成。通过改变-1\f25 VIA-1布局模式，单个LE可以输出12个逻辑，包括NOT、BUF、所有2输入逻辑功能、3输入AOI21和反相输出多路复用器(MUXI)。此外，Via-1版图还针对CP EB直写进行了优化。2007年，我们比较了VPEx与基于标准单元的ASIC和FPGA在面积、速度和功耗方面的性能。结果表明，VPEx的速度性能远好于现场可编程门阵列，比标准电池差约1.3-1.6倍。此外，我们还开发了采用VPEx架构的大规模集成电路测试芯片。该芯片所采用的工艺技术为0.18微米级。我们将在不久的将来对该芯片进行评估。

Integrated electronic system composed of microprocessors and large memories can be realized as a single chip owing to the progress of micro-fabrication technology of VLSI. The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool, because it is mask-less technology. The EB exposure time will be greatly reduced by applying character-projection (CP) EB direct writing. So we have developed new LSI device architecture appropriate for this CP EB direct-writing.In 2006, we proposed the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for CP EB direct writing.In 2007, we compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. Furthermore we developed LSI test chip which applying VPEX architecture. The process technology used in this chip is 0.18 urn CMOS. We will evaluate this chip in the near future.