Memory-based VLSI brain research for realizing recognition, learning and decision capability

开发了基于联想存储器的VLSI大脑功能核单元的算法、体系结构和集成电路。此外，还设计并测试了实际的VLSI测试芯片。“知识模式存储和最近距离搜索”单元的180 nm测试芯片实现了50-245 ns的搜索时间，功耗为36.5 mW，阳性检测率为99%。基于识别阈值、短期/长期存储和从先前识别的输入模式导出的参考模式更新的概念，开发了用于实现“获胜者读出和识别决定”、“模式学习”和“模式优化”单元的算法和集成电路。我们选择“手写字符识别”作为VLSI大脑开发的一个典型应用。通过参考数据优化算法，误分类从35%减少到9%。一款具有手写字符自动学习功能的超大规模集成电路脑测试芯片在100 MHz的频率下正确工作，在约2μ的时间内完成了S参考模式学习和优化的各个步骤，功耗为116 mW。

Algorithms, architectures and integrated-circuits of functional-core units for an associative-memory-based VLSI brain were developed. Additionally, actual VLSI test-chips were designed and measured. A 180nm CMOS test chip of the "knowledge-pattern storage and nearest-distance search" unit achieved 50-245ns search time, <36.5mW power consumption and >99% positive detection rate. The developed algorithms and integrated circuits for realizing the "winner readout and recognition decision", "patterns learning" and "pattern optimization" units are based on the concepts of a recognition threshold, short/long term storage and reference-pattern updates derived from the previously recognized input patterns. We selected "handwritten character recognition" as a representative application for performance evaluation of the developed VLSI brain. With the reference-data-optimization algorithms, misclassification was reduced from 35% to 9%. A VLSI-brain test chip with automatic hand-written-character learning capability functioned correctly up to 100MHz, completed each reference-pattern learning and optimization step in about 2μs and had a low power consumption of 116mW.