Low Power Techniques of Network-on-Chips for Many-core Computer Platforms

在这项研究中，我们的目标是提出创新的动态低功耗和低延迟技术的片上网络的众核处理器平台，形成IT设备，如移动的终端和高性能计算机。我们的主要解决方案是：（1）低功耗可变流水线和频率的片上路由器（1个周期到4个周期）优化流量负载，（2）它的动态重配置技术和（3）随机拓扑设计的路由器，其链路长度限制在6个核心逻辑长度。它们的效率通过全系统仿真和功率估计得到证实。

In this study our objective is to present innovative dynamic low-power and low-latency techniques of network-on-chips for many-core processor platforms that form IT equipments, such as mobile terminals and high-performance computers. Our main solutions are (1) low-power variable pipeline-and-frequency on-chip routers (1 cycle to 4 cycles) optimized to traffic load, (2) its dynamic reconfiguration techniques and (3) random topology design of routers whose link length is limited within 6 core logical length. Their efficiency is confirmed via full-system simulation and power estimation.