Study on Interconnect Integrity in Three Dimensional VLSI Systems

研究了三维超大规模集成电路系统的互连完整性，特别关注了硅通孔（TSV）和硅衬底之间的电耦合。开发了一个三维（3D）芯片堆叠的原型芯片，对其进行了测量和分析，以获得实验和分析的理解，并表明3D互连中的功率和衬底噪声耦合强烈依赖于芯片中tsv的物理位置和3D系统中电路的工作频率。采用片上噪声监测器和片上噪声仿真电路进行测量。用一个包含三维互连系统和硅衬底的等效电路进行了理论分析。测量和分析结果与三维VLSI原型芯片中噪声耦合的频率依赖性很好地吻合。这项工作是在IMEC（比利时）和神户大学（日本）的国际合作研究协议下进行的。

Interconnect integrity was studied for three dimensional VLSI systems, with a special focus on the electrical coupling between through silicon vias (TSV) and a silicon substrate. A prototype chip of three dimensional (3D) chip stacking was developped, measured, and analyzed for the experimental and analytical understanding, and showed that power and substrate noise coupling in a 3D interconnect was strongly dependent on the physical placements of TSVs in a chip and the operating frequency of circuits in a 3D system as well. The measurements were performed by using on-chip noise monitor and on-chip noise emulator circuits. The analysis was theoretically pursuied with an equivalent circuit involving 3D interconnect systems and a silicon susbtrate. The measurements and analysis agree well with the frequency dependency of noise coupling in a 3D prototype VLSI chip. This work was under the international collaborative research agreements between IMEC (Belgium) and Kobe University (Japan).