A method of high-level synthesis for multi-cycle transient fault tolerant digital systems

随着半导体技术的发展，由粒子撞击引起的瞬态故障越来越受到人们的关注，并且预计这种故障可能跨越多个时钟周期。本文根据操作间瞬时纠错和检错的操作单元的性质，提出了（1）一种基于纠错和检错性质的操作单元估计力的力导向调度算法;（2）一种以最小化操作单元数为目标，兼顾可纠错性和可检测性的绑定调度算法;以及（3）利用数据路径的可校正性/可检测性的用于合成瞬时容错控制器的方法。与简单的三重数据路径相比，该算法可以用较少的硬件资源推导出多周期容错系统。

As the advance in semiconductor technologies, transient faults caused by particle strike have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle.We proposes a high-level synthesis algorithm for long duration transient fault tolerance. On the basis of the properties of operational units for transient error correction and detection among operations, we present (1) a force-directed scheduling algorithm with the force derived from the estimation of operational units according to the properties of error correction and detection, (2) a binding algorithm aiming at achieving both of correctablility and detectability with minimizing the number of operational units, and (3) a method for synthesizing transient fault tolerant controllers that utilizes the correctability/detectability of datapaths. The proposed algorithm can derive multi-cycle fault tolerant systems with small hardware resources compared with simply-tripled datapaths.