Optoelectronic digital circuits based on resonant tunnelling diodes and photo diodes

本项目的目标是在不影响电路功能的情况下，减少数字光电接收电路中的器件数量、电路复杂性和功耗。为此，将使用PIN探测器二极管、共振隧穿二极管电路和晶体管放大器的单片集成。项目最后阶段的电路模拟表明，谐振隧穿二极管性能的显著提高导致了开关速度的显著提高。在成功地改善了共振隧穿二极管的性能之后，在该项目的第一阶段中还开发了用于电路模拟的器件模型。在下一阶段，应该使用阈值电压调节到共振隧穿二极管电压电平的异质结场效应晶体管，以便将新的光电解复用电路设计与新的高性能共振隧穿二极管匹配到50欧姆环境。这种新的电路设计具有更少的元件，将允许完整的1：2解复用而不会丢失数据，并且具有高数据速率。还将展示在50欧姆环境中级联成紧凑型1：N解复用器的过程。因此，我们将设计、制作和表征一个数据速率高达20Gbit/S、带输出缓冲的光电1：2解复用器演示器。还将评估增加功能和提高比特率至60Gbit/S的潜力。我们申请将该项目延长12个月。

The aim of this project is the reduction of the device count, circuit complexity and power dissipation in digital optoelectronic receiver circuits without any loss in circuit functionality. For this purpose, a monolithic integration of a PIN detector diode, a Resonant-Tunneling Diode circuit and a transistor amplifier will be used. Circuit simulations in the last phase of the project showed that, a considerable increase of the resonant tunneling diode performance leads to a significant improvement of switching speed. After this successful improvement of the resonant-tunneling diode performance, a device model for circuit simulation was also developed in the first phase of the project. In the next phase, a Heterostructure Field-Effect Transistor with threshold voltage, adjusted to the resonant-tunneling diode voltage level, should be used to match the new optoelectronic demultiplexer circuit design with the new high performance resonant tunneling diode to the 50 ohms environment. This new circuit design with fewer components shall allow a complete 1:2-demultiplexing without data loss and with high data rates. The cascading into compact 1: N demultiplexers in the 50-ohm environment will also be shown. As a result, an optoelectronic 1:2 demultiplexer demonstrator with data rate up to 20 Gbit/s with output buffer will be designed, fabricated and characterized. The potential to increased functionality and higher bit rates up to 60 Gbit/s will also be evaluated.We apply for 12 months extension of the project.