Collaborative Research: FuSe: Deep Learning and Signal Processing using Silicon Photonics and Digital CMOS Circuits for Ultra-Wideband Spectrum Perception

射频(RF)频谱编织着无线通信的结构。它是最珍贵和最稀缺的自然资源之一。未来的技术应用，如数字双胞胎、智能汽车和增强现实，需要随时随地进行千兆位每秒的无线连接。这样的需求需要有效的机制来保证高效和安全的射频频谱接入。现有的方法使用简单的技术，可以检测用户在频谱中的存在，但无法感知频谱的“谁、何时和如何使用”。尽管如此，新兴的人工智能(AI)方法，包括但不限于机器学习(ML)技术，在实现“射频感知”方面很有希望。在使用人工智能算法进行射频感知时，一个棘手的问题是无法处理频谱的大量感知带宽。为了解决这一问题，该项目将利用混合集成方法，将光子和电子小芯片或芯片协同结合，以促进在整个射频频谱上支持AI/ML的射频感知。该项目的教育部分将通过结合光子和电子芯片设计、AI/ML和无线技术技能的培训来解决美国半导体劳动力的匮乏问题。FUSE团队将在半导体、芯片设计和无线通信等主题上指导代表不足的女性和少数族裔。利用基于人工智能的项目接触高中生，将有助于建立一个渠道，让学生攻读专注于半导体和计算的工程学位。一个关键的教育重点是通过对模拟和数字IC设计课程的全面改造，对学生进行较新的FinFET节点的快速培训。PIS将在合作者之间共享开发的教育和培训材料，并将其在线提供。为了实现人工智能频谱感知，这一融合引信项目将与混合信号和高能效的异步数字芯片共集成光子集成电路，以实现实时的宽带射频感知。PIC前端将允许进行超过24 GHz带宽的射频频谱处理和信道化。混合信号IC将PIC的输出与数字AI加速器芯片连接。该团队将使用快速卷积神经网络创建AI/ML算法，用于无线物联网(IoT)设备或特定射频硬件前端的调制识别、频谱感知和检测。PIS将采用速度/功率效率高的RF处理核心的高级综合(HLS)技术，以实现实时AI/ML算法。这些HLS原型将针对最小芯片面积和功耗进行定制优化，并将使用权重量化、压缩处理、量化感知再训练、信号流图修剪和功率/面积优化的数字计算电路来实现低复杂性和快速吞吐量。该团队将把数字核心合成为异步数字芯片。最后，光子学和电子芯片将被带出，并使用最先进的商业铸造厂(包括基于FinFET的CMOS工艺)进行制造，然后打包进行测试和评估。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The radio frequency (RF) spectrum weaves the very fabric of wireless communications. And it is among the most precious and scarcest of natural resources. Tomorrow’s tech applications such as digital twins, smart vehicles, and augmented reality demand Gigabit-per-second wireless connectivity everywhere all the time. Such demands call for effective mechanisms to guarantee efficient and secure RF spectrum access. Existing methods use simple techniques that can detect users' presence in the spectrum but cannot sense the “who, when, and how” of the spectrum being utilized. Nonetheless, emerging artificial intelligence (AI) methods including but not limited to machine learning (ML) techniques are promising for achieving “RF perception.” A thorny problem in using AI algorithms for RF perception is the inability to process the massive sensed bandwidth of the spectrum. To solve this problem, this project will leverage a hybrid integration approach, where photonic and electronic small chips, or chiplets, will be synergistically combined to facilitate AI/ML-enabled RF perception over the entire RF spectrum. The education component of the project will address the dearth in the US-based semiconductor workforce through a combination of training on photonic and electronic chip design, AI/ML, and wireless technology skills. The FuSe team will mentor women and minorities who are underrepresented, in topics such as semiconductors, chip design, and wireless communication. Outreach to high-school students using AI-based projects will help build a pipeline of students to pursue engineering degrees focusing on semiconductors and computing. A critical educational emphasis is to fast-track training of students on newer FinFET nodes through a complete revamp of analog and digital IC design courses. The PIs will share the developed education and training material amongst the collaborators and make them available online.To achieve AI-enabled spectrum sensing, this convergent FuSe project will co-integrate a photonic integrated circuit (PIC) with mixed-signal and energy-efficient asynchronous digital chiplets to realize real-time wideband RF perception. The PIC front-end will allow RF spectrum processing and channelization of over 24 GHz of bandwidth. The mixed-signal IC will interface the PIC’s output with digital AI accelerator chiplets. The team will create AI/ML algorithms for modulation recognition, spectrum sensing, and detection of wireless internet-of-things (IoT) devices or specific RF hardware front-ends using fast convolutional neural networks. PIs will employ high-level synthesis (HLS) of speed/power-efficient RF processing cores for real-time AI/ML algorithm implementation. These HLS prototypes will be custom optimized for minimum chip area and power consumption and will achieve low complexity and fast throughput using weight quantization, compressive processing, quantization-aware retraining, signal flow graph pruning, and power/area-optimized digital computing circuits. The team will synthesize the digital cores as asynchronous digital chiplets. Finally, the photonics and electronic chiplets will be taped-out and fabricated using state-of-the-art commercial foundries including the FinFET-based CMOS process, and then packaged for testing and evaluation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.