低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出
低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出
批准号:
13J08817
负责人:
ハサンザデ ダリューシュ
金额:
$1.32万
依托单位国家:
日本
项目类别:
Grant-in-Aid for JSPS Fellows
财政年份:
2013
资助国家:
日本
项目状态:
已结题
起止时间:
2013 至 2014
中文摘要
这项研究的重点是了解和设计High-k和InGaAs的接口,以实现移动设备中应用的低功耗、高性能设备。本研究选用稀土氧化物La203作为高k氧化物。高k/InGaAs界面面临的主要问题是不稳定氧化物的形成,这导致了几种类型的缺陷的形成,如氧化物和衬底中的界面陷阱(DIT)和体陷阱。然而,由于LaInGaO界面层的形成,用La203可以制备出极低的缺陷界面。这种界面层具有非晶态性质,防止了不稳定氧化物的形成,从而提高了界面质量。通过本研究中进行的La203在InGaAs上的原子层沉积(ALD),报道了InGaAs衬底上最小等效氧化层厚度的最低DIT,其数值为小于10的11次方。由于FinFET设计在…中的流行在较新的器件结构中,评估不同取向的InGaAs衬底上La203界面的特性是很重要的。与平面器件结构相反,FinFET器件中的器件沟道区由多个取向组成。因此,为了从FinFET设计的卓越静电栅极特性中获益,在所有衬底取向上实现高质量的界面非常重要。在本研究中,我们在[100],[110]和[111]取向的InGaAs衬底上制备了ALD沉积La203氧化物的MOSFET。在MOSFET中使用的所有p型基板都具有预先形成的源区和漏区。结果发现,在所有的衬底上都可以获得类似的DIT。所有MOSFET的亚阈值摆幅为~130 mV/dec,这意味着相似的界面特性。然而,对于[111]取向的衬底,获得了更高的漏电流和跨导值。这种效应可能与该表面较低的电子有效质量有关,这是晶体表面的一种材料特性。这些结果显示了La203在工业中各种InGaAs器件中的应用潜力。较少
英文摘要
This research focuses on understanding and engineering the interface at high-k and InGaAs for enabling low power, high performance devices for application in mobile devices. Rare metal earth oxide La203 is chosen as the high-k oxide in this research. The main issues facing high-k/InGaAs interface, is the formation of unstable oxides which lead to formation of several types of defects such as interface traps (Dit) and bulk traps within both the oxide and substrate. However, it was found that extremely low defect interfaces can be fabricated by using La203 due to formation of LaInGaO interfacial layer. This interfacial layer has an amorphous nature and prevents the formation of unstable oxides, thus improving the quality of the interface. Lowest reported Dit on smallest equivalent oxide thickness on InGaAs substrates in the order of lower 10 to the power of 11 was reported by atomic layer deposition(ALD) of La203 on InGaAs conducted in this research. Due to prevalence of finFET design in … More recent devices structures, it is important to evaluate the characteristics of La203 interface on various orientations of InGaAs substrate. Contrary to a planar device structure, the device channel region in a FinFET device is composed of multiple orientations. Therefore, it is important to achieve high quality interface on all substrate orientations in order to benefit from the superior electrostatic gate properties of the finFET designs. In this research, MOSFETs with ALD-deposited La203 oxide on [100], [110] and [111] oriented InGaAs substrates were fabricated. All p-type substrates used in MOSFETs had pre-formed source and drain regions. It was found that a similiar Dit can be achieved on all substrates. The substhreshold swing in all MOSFETs was ~130 mV/dec which imply similar interface characteristics. However, higher drain current and transconductance values were achieved for the substrate with [111] orientation. This effect could be related to lower effective mass of electrons in this surface which is a material property of crystalline surface. These resutls show the potential for using La203 in various InGaAs devices in idustry. Less
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会议论文
Scalable La-silicate Gate Dielectric on InGaAs Substrate with High Thermal Stability and Low Interface State Densit
InGaAs 衬底上的可扩展硅酸铝栅极电介质,具有高热稳定性和低界面态密度
DOI:
--
发表时间:
2013
期刊:
影响因子:
--
作者:
[J. Naganawa, et al., Daryoush Hassan Zadeh, Daryoush Hassan Zadeh]
通讯作者:
Daryoush Hassan Zadeh
Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction
低 Dit 高 k/In0.53Ga0.47As 栅极堆叠,CET 低至 0.73 nm,通过抑制界面反应实现热稳定硅化物接触
DOI:
10.1109/iedm.2013.6724544
发表时间:
2013
期刊:
2013 IEEE International Electron Devices Meeting
影响因子:
--
作者:
[D. Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai]
通讯作者:
H. Iwai