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BIST for Intelligent Self-Testing of Integrated Circuits at Manufacture and In-Life

BIST for Intelligent Self-Testing of Integrated Circuits at Manufacture and In-Life
用于制造和使用过程中集成电路智能自测试的 BIST
批准号:
102015
负责人:
金额:
$42.73万
依托单位:
依托单位国家:
英国
项目类别:
Collaborative R&D
财政年份:
2015
资助国家:
英国
项目状态:
已结题
起止时间:
2015 至 --

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中文摘要
翻译
全球半导体行业在测试数据转换器(ADC和DAC)方面面临重大挑战,它们占用研发资源并限制最高规格产品的发布。Ateeda已经(通过最近完成的SMART可行性研究)在模拟中演示了一种用于ADC和DAC的内置自检(BIST)的新方法。两项核心创新目前正在申请专利,允许进行高精度(例如音频)转换器BIST。Ateeda将与兰开斯特大学合作,降低技术风险,并在硅中验证这种方法是否符合商业需求。由此产生的演示将使客户相信这将转化为制造环境,从而实现商业评估和购买。高精度模拟BIST是一个重要的市场机会,Ateeda在该项目成功完成后处于有利地位,但风险太高,无法证明否则开发是合理的。
英文摘要
The global semiconductor industry faces major challenges in testing data converters – ADCs and DACs –occupying R&D resources and constraining release of highest specification products. ATEEDA has demonstrated (via a recently completed SMART feasibility study) a new approach to Built-In Self-Test (BIST) for ADCs and DACs in simulation. Two core innovations are now patent-pending, permitting high-precision (e.g. audio) converter BIST. ATEEDA will work with Lancaster University to mitigate technical risks and validate in silicon that this approach meets commercial requirements. The resultant demonstrator will give customers confidence that this will translate into a manufacturing environment, enabling commercial evaluation and purchase. High-precision Analogue BIST is a significant market opportunity ATEEDA is well positioned to exploit following successful completion of this project, but where the risks are too high to justify development otherwise.
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  • 批准号:
    --
  • 项目类别:
    外国学者研究基金项目
  • 资助金额:
    --
  • 批准年份:
    2024
  • 负责人:
    USHARANI HAREESH GOVINDARA JAN
  • 依托单位: