A bidirectional power/data transfer platform based on electro-optical effects in standard CMOS

随着近年来芯片实验室应用需求的激增，对不同技术，特别是CMOS/MEMS和微流体的低成本集成的需求变得至关重要。特别是由半导体行业驱动的规模经济倾向于基于未经修改的商业流程的解决方案。不同组件的物理尺寸变化范围所决定的限制使得晶圆级集成对于低成本的大规模生产来说过于昂贵。例如，典型的片上实验室应用可能需要面积为1-10平方的CMOS元件。mm， MEMS元件在25-100平方的区域。Mm和微流体元件在200-2500平方区域。因此，将这些集成到晶圆级对于CMOS/MEMS技术来说将是巨大的浪费，因为常见的片上实验室区域将受到连接流体和外部系统到设备的要求的限制。在模具级别集成这些组件的常用技术，例如在化学传感中，包括以下顺序。将导线将芯片粘合到封装或基板上，将导线粘合在绝缘材料中，使顶部表面平整，通过密封剂对（芯片表面）的传感区域进行图案化，最后对准并铺设微流体层。这种方法的主要挑战都与键合线突出于传感表面的事实有关。除了导致关键的可靠性问题外，表面几何形状也受到了极大的影响，即在粘结垫区域内产生了不需要的井，并且顶部表面（封装剂上方）远离平面，导致密封，从而在覆盖微流体时产生可靠性问题。本文提出了一种新的集成方法。我们的想法是开发一种方法，在没有任何键合线的情况下与CMOS芯片接口，使芯片顶部表面保持平面，没有键合板开口。因此，挑战在于开发一种技术：(1)向CMOS芯片提供电源和控制信号，(2)以非接触方式将数据从CMOS芯片传输到外部设备。此外，没有片外连接的另一个挑战是不能使用片外组件，例如天线或电容器，例如RFID的情况。因此，我们建议在混合PCB/CMOS组件中应用光学技术，使顶部表面几乎保持平面，所有外部组件都安装在CMOS芯片下方。该方案打算通过一个红外（IR）发射器通过硅提供电源和控制，使用一个相对大面积的深井光电二极管来恢复功率和数据。因此，透射光（即未被吸收的光子）可以使用电光效应进行调制，并通过芯片反射回安装在CMOS芯片下方的探测器。因此，可以使用相对简单的离散电子器件从接收到的信号中提取数据。虽然该方案最初是用于混合，芯片上的实验室应用，但更广泛的开发范围是巨大的，影响整个微电子工业的应用基础。

With the recent surge in the demand for lab-on-chip applications, the requirement for a low-cost integration of different technologies, in particular CMOS/MEMS and microfluidics has become crucial. Economies-of-scale especially driven by the semiconductor industry favour solutions based on unmodified commercial processes. The constraints dictated by the varying range of physical dimensions of the different components make wafer-level integration too costly for low-cost mass manufacture. For example, a typical lab-on-chip application may require CMOS components of area in the region of 1-10 sq. mm, MEMS components in the region of 25-100 sq. mm and microfluidics components in the region of 200-2500 sq. mm. Therefore integrating these at wafer level would be hugely wasteful to CMOS/MEMS technologies, as the common lab-on-chip area would be constrained by the requirement of interfacing fluids and external systems to the devices. A common technique for integrating these components at die-level, for example in chemical sensing, includes the following sequence. Wire bonding the chip to a package or substrate, encapsulating the wire bonds in an insulating material, levelling off the top surface, patterning the sensing regions (on chip surface) through the encapsulant, and finally aligning and laying on the microfluidics layers. The main challenges to this approach are all related to the fact that the bond wires are protruding above the sensing surface. In addition to this resulting in crucial reliability issues, the surface geometry is vastly affected, i.e. unwanted wells are created inside the bond pad regions and, the top surface (above the encapsulant) is far from planar- resulting in sealing and thus reliability issues when overlaying the microfluidics. A novel solution to this integration problem is proposed here. The idea is to develop a methodology for interfacing to CMOS chips without any bond wires such that the top chip surface is left planar with no bondpad openings. The challenge is therefore to develop a technique to: (1) provide power and control signals to a CMOS chip and (2) communicate data from the CMOS chip to an external device in a contactless fashion. Furthermore, an added challenge of having no off-chip connections is that no off-chip components, for example, antennas or capacitors can be used- such as in the case of RFID's. We therefore propose to apply optical techniques in a hybrid PCB/CMOS assembly such that the top surface is left virtually planar with all external components being mounted underneath the CMOS die. The scheme intends to supply power and control via an infrared (IR) emitter through the silicon using a relatively large area deep well photodiode to recover power and data. The transmitted light (i.e. non-absorbed photons) can therefore be modulated using electro-optical effects and reflected back through the die to a detector mounted beneath the CMOS die. The data can therefore be extracted from the received signal using relatively simple discrete electronics. Although this scheme is initially intended for hybrid, lab-on-chip applications, the wider scope for exploitation is enormous, with an impacting application-base throughout the microelectronics industry.