Automating ISA support for Design Space Exploration

模拟ISA的架构设计和性能分析提供了一个平台，以帮助设计一个接近最佳的处理器，为给定的一组可用的技术，但这项任务是不平凡的。目前需要做大量的工作来为几种架构提供支持，例如最近支持的RISC-VISA，通过我在JSC的研究，我发现RISC-VISA很有前途，但还不够成熟，无法广泛采用。自动化这个过程将允许大量的新架构一旦通过Sail发布就可以得到支持，Sail是一种可以为给定处理器提供执行逻辑的语言[1]。这为未来的基准测试，优化和比较几个现代架构的工作打开了大门，而无需手动添加支持的易出错工作。

Simulating ISAs for both architectural design and performance analysis provides a platform to help design a near-optimal processor for a given set of available technology, but this task is not trivial. Significant work is currently required to provide support for several architectures such as the recently supported RISC-VISA, one that I found promising but not yet mature enough for wide spread adoption through my research at the JSC. Automating this process would allow for a significant number of new architectures to be supported once released via Sail, a language that can provide the execution logic for a given processor[1]. This opens the door for future work of benchmarking, optimising and comparing several modern architectures without the error-prone work of adding support manually.