EDA tools for strained Si CMOS cell libraries with variability models

世界半导体市场每年以数十亿美元计，其中80%由互补金属氧化物半导体（CMOS）主导，有趣的是，Si器件占所有微电子器件的97%。逐渐小型化已成为芯片中晶体管密度稳步增加的驱动方法。预计到2020年后，该行业的规模将是目前的25倍，一年的增长将超过今天整个行业的增长。CMOS器件的频繁收缩是这种增长的关键，只要行业以更快的速度增长，这种增长就可能持续下去。然而，逐渐小型化的方法正受到器件和材料物理的挑战。为了迎接挑战，研究人员开始寻找替代品。这种替代方案之一是用应变Si取代MOS器件中的Si沟道。应变Si沟道可以提供非常高的性能水平，而无需积极的缩放，保持其与传统CMOS工艺的兼容性。硅中的应变工程是未来CMOS技术的关键特征，其在CMOS器件中的益处在很大程度上是对可能的缩放影响的附加。自上个十年以来，应变硅中的性能增强超过其硅对应物一直在进步。在体硅衬底上生长的厚SiGe层形成虚拟衬底（VS）。当随后在VS的顶部上生长Si薄膜时，其处于拉伸应变下。在硅沟道中引入应变改善了其载流子输运特性，从而导致高速器件。然而，它还没有可能的设计社区，以利用应变硅的器件级性能的改善。应变硅器件的巨大潜力只有在不同层次的面向应用的逻辑电路/块中才能充分发挥。这就需要开发以应变硅CMOS器件为基本单元的前端电子设计自动化（EDA）工具。在学术界或工业界没有这样的单元库或EDA工具，因此，迫切需要一个研究计划来弥合技术和设计社区之间的差距。此外，MOSFET参数的变化一直是电路设计人员面临的挑战，因为这些变化会导致I-V曲线、功耗、时序分析的不确定性，甚至导致电路故障。在应变Si技术中，由于更高水平的材料和器件水平可变性（诸如更高的缺陷和陷阱、表面粗糙度和Ge浓度），可变性将甚至大于常规Si。因此，还需要进行旨在模拟和表征工艺、器件和电路层面变化的研究。这项研究计划解决了世界上第一个示范应变硅/硅锗基单元库的前端EDA工具。这也在设计中纳入了工艺和器械水平的可变性。该研究提案将弥合技术和设计界之间的差距，并将为设计界提供机会，以开发应变硅为基础的超大规模集成电路，有助于加快应变硅技术的生产实施。

The world market for semiconductors is counted in billions of dollars per year in which 80% of it is dominated by complementary metal oxide semiconductor (CMOS) and interestingly, Si devices account for 97% of all microelectronics. Gradual miniaturization has been the driving methodology for the steady increament of density of transistors in a chip. The industry is projected to be 25 times the present size after 2020 where one year's growth would be larger than today's entire industry. The frequent shrinking of CMOS devices is the key for this growth and it is likely to be continued as long as the industry grows at a significantly faster rate. However, the Gradual miniaturization methodology is being challenged by the device and material physics. To meet the challenge, research began to look for alternatives. One of such an alternatives is the replacement of Si channel in MOS devices by strained Si. The strained Si channel can deliver a very high level of performance without aggressive scaling maintaining its compatibility with the conventional CMOS process. Strain engineering in Si is a crucial feature for future CMOS technology and its benefit in CMOS devices is largely additive to the impact of possible scaling. Since last decade, performance enhancement in strained Si over its Si counterpart has progressed consistently. A thick layer of SiGe grown on a bulk Si substrate forms the virtual substrate (VS). When a thin film of Si is subsequently grown on top of the VS, it is under tensile strain. Introduction of strain in Si channel improves its carrier transport property resulting to high speed devices. However, it has not yet been possible for the design community to exploit the device level performance improvement in strained Si. The enormous potential of strained Si devices can only be extracted fully if it is used at different levels of application oriented logic circuits/blocks. This requires developing front end Electronic Design Automation (EDA) tools with strained Si CMOS devices as the basic units. No such cell libraries or EDA tools are available in academia or industry, and hence, a research program is urgently needed to bridge this gap between the technology and design community. Moreover, the variations in MOSFET parameters have always been a challenge for circuit designers since these variations cause uncertainty in I-V curves, power dissipation, timing analysis, and even leading failure in circuits. In strained Si technology, variability will be even greater than conventional Si due to the higher level of material and device level variability such as higher defects and traps, surface roughness and Ge concentrations. Thus, research aimed at modelling and characterising variations at process, device and circuit levels is also needed. This research proposal addresses the world's first demonstration of strained Si/SiGe based cell libraries for front end EDA tools. This also incorporates process and device level variability in the design. The research proposal will bridge the gap between technology and design community and will provide opportunity to the design community to develop strained Si based VLSI circuits helping to expedite the implementation of strained Si technology into production.