Reconfigurable Architecture Design: An Optimization Approach

这个建议是关于可重构体系结构的自动设计。所提出的方法形成了一个从标准的工业和学术实践中的可重构架构设计的根本出发。这种方法的主要特点是它的基础上正式的全局优化程序从数学规划和运筹学社区，在通常用于攻击这个问题的经验方法，其目的是开发和扩展的功耗，计算吞吐量和硅面积使用的数学模型，并将这些在一个数学规划框架。这将允许同时优化多个架构和综合参数，导致可证明质量的解决方案，并消除由此产生的架构对启发式偏差的依赖。已经取得了有希望的初步结果，提供了可证明的最佳界限的相对计算速度的各种DSP基准相比，ASIC实现相同的电路，并提出架构，导致高达20%的速度提高（对于相同的面积）或60%的面积减少（对于相同的速度）比商业架构。资金要求博士后研究助理（3年）和博士。学生（3.5岁）与研究人员一起工作。

This proposal is concerned with the automatic design of reconfigurable architectures. The proposed approach forms a radical departure from standard industrial and academic practice in reconfigurable architecture design. The main feature of this approach is its basis in formal global optimization proceduresfrom the mathematical programming and operations research communities, in contrast to the empirical approaches typically used to attack this problem.The intention is to develop and extend mathematical models of power consumption, computation throughput, and silicon area usage, and incorporate these within a mathematical programming framework. This will allow the simultaneous optimization of multiple architectural and synthesis parameters, leading to provable-quality solutions, and eliminating the dependence of the resulting architecture on heuristic bias.Promising preliminary results have already been achieved, providing provably optimal bounds on the relative computational speed of various DSP benchmarks compared to ASIC implementations of the same circuits, and proposing architectures resulting in up to 20% speed improvement (for the same area) or 60% area reduction (for the same speed) over commercial architectures.Funding is requested for a post-doctoral research associate (3 years) and a Ph.D. student (3.5 years) to work with the investigators.