Real-time Numerical Optimization in Reconfigurable Hardware with Application to Model-Predictive Control

该方案涉及迭代数值算法的硬件加速，重点是模型预测控制的实现。这种模型预测控制器通常需要在每个采样周期内求解二次规划问题。二次规划问题的求解通常需要几个多维牛顿优化，每个多维牛顿优化都需要求解许多线性方程组。因此，所学到的经验将适用于在控制内外的实际问题中出现的广泛类别的数值算法。从数字电子学的角度来看，该方法的主要冒险特征是潜在地使用控制和系统理论来告知定制可重构计算中的核心设计问题之一：通过适当的有限精度数字表示来高效地利用硅。在顺序(单核)计算机体系结构中，通过引入面积昂贵的高精度IEEE兼容算术单元，基本上已经回答了数值精度的问题。在现代计算系统中，无论是基于现场可编程门阵列还是多核计算系统，人们的注意力正转向如何最有效地利用可用于计算的硅，在这种背景下，数值精度要求的问题再次出现。所提出的方法从根本上背离了模型预测控制(MPC)和数字电子技术的标准工业和学术实践。从终端用户的角度来看，这种方法的主要创新之处在于利用可重构的硬件设备，即现场可编程门阵列(现场可编程门阵列)来实现在高采样率下运行的模型预测控制器，使得预测控制可以用于到目前为止被认为计算负荷太大的应用领域，如航天器、飞机、无人自动驾驶车辆、汽车控制系统和燃气轮机。从理论的角度来看，控制的主要冒险是开发明显利用并行计算体系结构的新公式。解决这一问题的方法学的发展将涉及将控制理论思想应用于硬件开发以及将硬件实现方法学应用于控制系统设计的高度新颖的研究领域。特别是，该建议是第一个研究大规模并行实时数值优化的现场可编程门阵列，第一个应用控制理论技术来确定定制硬件设计中合适的数字系统，以及第一个研究闭环行为环境中电路并行性和数值精度之间的权衡。因此，该建议直接落入EPSRC最近发布的微电子大挑战3-Moore for Lost的范围内。

This proposal is concerned with the hardware acceleration of iterative numerical algorithms, with a focus on model predictive control implementations. Such model predictive controllers typically require the solution of a quadratic progamming problem every sample period. The solution of the quadratic programming problem typically requires several multidimensional Newton optimizations, each of which requires the solution of many systems of linear equations. Thus the lessons learned will be applicable to a wide class of numerical algorithms arising in practical problems within and beyond Control.The main adventurous feature of the approach from the digital electronics perspective is the potential to use Control and Systems theory to inform one of the central design problems in custom reconfigurable computing: efficient silicon utilization through appropriate finite precision number representation. In sequential (single core) computer architecture, questions of numerical precision have, by and large, been answered through the introduction of area costly high-precision IEEE compliant arithmetic units. In modern computing systems, whether FPGA-based or manycore, attention is now turning to how to make the most effective use of the silicon available for computation and, in this context, questions of numerical accuracy requirements are arising once more.The proposed approach forms a radical departure from standard industrial and academic practice in both model predictive control (MPC) and digital electronics. The main adventurous feature of the approach from the end-user perspective is the utilization of reconfigurable hardware devices, namely Field-Programmable Gate Arrays (FPGAs), to implement model predictive controllers operating at high sample rates, allowing MPC to be utilized in application areas where the computational load has been considered too great until now, such as spacecraft, aeroplanes, uninhabited autonomous vehicles, automobile control systems and gas turbines. From the theoretical perspective, the main adventure in Control is in the development of novel formulations that explcitly take advantage of parallel computational architectures.The development of a methodology to tackle this problem will involve highly novel research areas resulting from the application of control theoretic ideas to hardware development, as well as the application of hardware implementation methodologies to control system design. In particular, this proposal is the first to investigate massively parallel real-time numerical optimization on FPGAs, the first to apply control-theoretic techniques to determine appropriate number systems in custom hardware designs, and the first to study the tradeoff between circuit parallelism and numerical accuracy within a closed-loop behavioural context.As a result, this proposal directly falls within the scope of EPSRC's recently signposted Microelectronics Grand Challenge 3 - Moore for Less.