FuSe-TG: The Future of Semiconductor Technologies for Computing through Device-Architecture-Application Co-Design

《麻省理工学院技术评论》2020年的一期文章写道：[摩尔定律]推动了过去50年的繁荣。但末日现已指日可待。然而，后一种结论值得商榷。在历史上，半导体的指数级增长是通过器件(晶体管、存储器和导线)的二维(2D)小型化来实现的，以便在相同的芯片区域中封装更多组件并实现更低的每功能成本。事实上，我们现在正在达到这种2D扩展范例的物理极限。然而，替代方法将引发重振美国半导体经济的巨大转变。该项目将通过大学和半导体行业/行业研究领导者之间的伙伴关系，通过教育努力将新知识转化为教育渠道和半导体劳动力，以及通过试验新的合作方法，使实验室到工厂的翻译更容易地与行业专家的强有力的投入，来探索、确定和规划未来的可能道路。因此，这项合作拨款将为用于特定领域计算的半导体的未来开辟新的基础。更长期的目标是通过鼓励学生在国家制造厂附近的半导体行业走上职业道路，在研究、教育和商业化方面产生全国性的影响。这是通过多个催化剂来计划的，例如，针对社区大学生的实验室和工厂体验的试点计划、联合设计挑战等。在过去20年中，创建彼此独立的架构和设备技术变得越来越站不住脚，因为存在跨越抽象边界的相互交织的依赖关系。此外，由于未来系统对能源效率的极端需求，架构和设备技术必须由手头的特定应用领域驱动。因此，本项目的重点是设备-架构-应用的协同设计。在三维(3D，就像高楼)中构建，在3D层之间具有超密集的垂直连接，可以以可扩展的方式显著增加封装在一块芯片上的设备的数量，从而在能源和吞吐量方面获得显著的好处，例如，斯坦福纳米工程计算系统技术(N3XT)3D方法所使用的。多个N3XT 3D芯片将通过芯片堆叠/插入器/晶圆级组装/集成的连续体进行集成。这一合作活动的基础将是单片堆叠、组装的IC(马赛克)N3XT 3D概念。与仅仅依赖硅基晶体管来执行所有期望的功能不同，将使用经优化设计以执行各种/不同功能的异质材料和定制的器件结构，即特定于领域的器件技术。该项目将探索新的特定领域的架构(例如，针对AI深度神经网络、增强现实/虚拟现实和图形分析)，这些架构由技术概念、新的电子设计自动化工具和新的开放源码框架实现，用于设备-架构-应用程序的联合设计。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

A 2020 issue of Massachusetts Institute of Technology’s Tech Review read “[Moore’s law] has fueled prosperity of the last 50 years. But the end is now in sight.” However, this latter conclusion can be debated. Historically, exponential growth in semiconductors was achieved through two-dimensional (2D) miniaturization of devices (transistors, memory, and wires) to pack more components in the same chip area and achieve lower cost per function. Indeed, we are now reaching the physical limits of this 2D scaling paradigm. However, alternative approaches will trigger a seismic shift to reinvigorate the US semiconductor economy. This project will explore, identify, and map out the possible paths that lie ahead through partnerships among universities and industry/industrial research leaders in semiconductors, through educational efforts to translate new knowledge into the educational pipeline and semiconductor workforce, and through piloting new collaboration methods to enable lab-to-fab translation more readily with robust inputs from industry experts. This teaming grant will thus break new grounds for the future of semiconductors for domain-specific computing. The longer-term goal is to create national impact on research, education, and commercialization by encouraging students to follow a career path in semiconductors near national fab facilities. This is planned through multiple catalysts, e.g., a pilot program for lab and fab experiences for community college students, co-design challenges etc.In the past two decades, it has become increasingly untenable to create architectures and device technologies independent of one another because there are intertwined dependencies across the abstraction boundaries. In addition, because of the extreme energy efficiency demands of future systems, architectures and device technologies must be driven by the specific application domains at hand. Thus, the focus of this project is device-architecture-application co-design. Building in the third dimension (3D, like a high-rise), with ultra-dense vertical connectivity between 3D layers, could significantly increase the number of devices packed on a piece of chip real estate in a scalable manner for significant benefits in energy and throughput, as, e.g., used by the Stanford Nano-Engineered Computing Systems Technology (N3XT) 3D approach. Multiple N3XT 3D chips are to be integrated through a continuum of chip stacking-/interposer-/wafer-level assembly/ integration. The foundation for this teaming activities will be the MOnolithic Stacked, Assembled IC (MOSAIC) N3XT 3D concept. Rather than relying solely on silicon-based transistors to perform all desired functions, heterogeneous materials and customized device structures optimally designed to perform diverse/distinct functions, i.e., domain-specific device technologies, will be used. The project will explore new domain-specific architectures (e.g., targeting AI deep neural nets, augmented reality/virtual reality, and graph analytics) uniquely enabled by the technology concepts, new Electronic Design Automation tools, and new open-source frameworks for device-architecture-application co-design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.