FuSe-TG: The Future of Semiconductor Technologies for Computing through Device-Architecture-Application Co-Design

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A 2020 issue of Massachusetts Institute of Technology’s Tech Review read “[Moore’s law] has fueled prosperity of the last 50 years. But the end is now in sight.” However, this latter conclusion can be debated. Historically, exponential growth in semiconductors was achieved through two-dimensional (2D) miniaturization of devices (transistors, memory, and wires) to pack more components in the same chip area and achieve lower cost per function. Indeed, we are now reaching the physical limits of this 2D scaling paradigm. However, alternative approaches will trigger a seismic shift to reinvigorate the US semiconductor economy. This project will explore, identify, and map out the possible paths that lie ahead through partnerships among universities and industry/industrial research leaders in semiconductors, through educational efforts to translate new knowledge into the educational pipeline and semiconductor workforce, and through piloting new collaboration methods to enable lab-to-fab translation more readily with robust inputs from industry experts. This teaming grant will thus break new grounds for the future of semiconductors for domain-specific computing. The longer-term goal is to create national impact on research, education, and commercialization by encouraging students to follow a career path in semiconductors near national fab facilities. This is planned through multiple catalysts, e.g., a pilot program for lab and fab experiences for community college students, co-design challenges etc.In the past two decades, it has become increasingly untenable to create architectures and device technologies independent of one another because there are intertwined dependencies across the abstraction boundaries. In addition, because of the extreme energy efficiency demands of future systems, architectures and device technologies must be driven by the specific application domains at hand. Thus, the focus of this project is device-architecture-application co-design. Building in the third dimension (3D, like a high-rise), with ultra-dense vertical connectivity between 3D layers, could significantly increase the number of devices packed on a piece of chip real estate in a scalable manner for significant benefits in energy and throughput, as, e.g., used by the Stanford Nano-Engineered Computing Systems Technology (N3XT) 3D approach. Multiple N3XT 3D chips are to be integrated through a continuum of chip stacking-/interposer-/wafer-level assembly/ integration. The foundation for this teaming activities will be the MOnolithic Stacked, Assembled IC (MOSAIC) N3XT 3D concept. Rather than relying solely on silicon-based transistors to perform all desired functions, heterogeneous materials and customized device structures optimally designed to perform diverse/distinct functions, i.e., domain-specific device technologies, will be used. The project will explore new domain-specific architectures (e.g., targeting AI deep neural nets, augmented reality/virtual reality, and graph analytics) uniquely enabled by the technology concepts, new Electronic Design Automation tools, and new open-source frameworks for device-architecture-application co-design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.