Methods for the design and testing of digital systems

研究的主要领域涉及有限状态机的设计和使用，作为生成器构建在芯片上，以提供芯片上系统的内置自测试。我们已经提出了元胞自动机寄存器（CAR）的替代线性反馈移位寄存器在一些应用中，因为，虽然他们是类似的线性反馈移位寄存器从理论的角度来看，他们产生的位序列，导致改进的测试行为。我们早期的工作导致了唯一实用的算法，这些机器的综合。然而，很明显，将它们修改为略微非线性，可以提高测试性能。这种机器的设计和分析是相当复杂的，因为我们缺乏一些分析工具，拟议的研究将继续与CAR的发展和其他非线性机器的基础研究。我们的第二个方向是去年在可逆逻辑领域开发的新方向。 它从25年前我们在电路设计的限制原语方面的一些早期工作开始。由于冯·诺依曼/朗道尔原理，即正常（不可逆）逻辑运算产生基本的最小能量成本，这一点最近变得越来越重要。这一成本有可能在未来15到20年内终止计算机实际性能的改进。然而，已经证明，基于可逆逻辑运算的计算机可以重用一小部分信号能量（理论上，这一部分可以接近100%），这使我们有可能在指定的功耗水平内继续任意提高计算机性能。为了实现这一点，我们必须开发高度优化的可逆逻辑电路的设计和测试算法。这是我们第二个研究领域的目标。

The major area of study concerns the design and uses of Finite State Machines as generators to build onto a chip to provide built-in self-testing of the system on the chip. We have proposed Cellular Automata Registers (CAR) as alternatives to linear feedback shift registers in a number of applications, since, while they are similar to linear feedback shift registers from a theoretical perspective, they generate bit sequences that lead to improved testing behaviour. Our earlier work has led to the only practical algorithm for the synthesis of these machines. However, it is clear that modifying them to be slightly non-linear, gives improved performance for testing. The design and analysis of such machines is considerably more complex, since we lack some of the analytical tools, and the proposed research will continue both with the development of CAR and underlying research into other non linear machines. Our second direction is a new one developed over the last year in the area of reversible logic.  It picks up on some of our earlier work from 25 years ago on restricted primitives for the design of circuits. This are has become of rapidly increasing importance rcently because of the von Neumann/Landauer principle that normal (non reversible) logic operations incur a fundamental minimum energy cost. This cost threatens to end improvements in practical computer performance within the next 15 to 20 years. However, it has been proved that computers based on reversible logic operations can reuse a fraction of the signal energy (in theory, this fraction can approach 100%) that gives us the possibility of continuing to arbitrarily improve computer performance within a specified level of power dissipation. For this to be feasible, we have to develop algorithms for the design and testing of highly optimized reversible logic circuits. This is the goal of our second research area.