Frontiers-based synthesis of digital logic

硬件描述语言（HDL）一直停留在较低的语义层次，抽象能力有限。这些特点使得VLSI asic和fpga的开发变得更加困难和昂贵。对编程语言及其语义的研究已经建立了一条通往规范/实现语言的道路，这些语言具有更清晰的语义和强大的抽象能力。众所周知，这种语言可以改进硬件描述、合成和验证的过程。但是缺乏一种方法来弥合更强大的语言和布尔门之间的巨大语义差距，阻碍了这个方向的实际进展。然而，申请人和前博士生的工作已经建立了一种有效的方法，从这些抽象语言合成最小的门实现。该方法基于扩展布尔域边界的计算。建议的工作将：a)改进早期工作的理论基础；b)使规范语言更丰富并支持合成器中的新功能；c)将该规范语言嵌入Verilog中，以便完整的Verilog工具链可以用于实验；d)从长远来看，将该语言扩展到异步设计领域，这是VLSI社区迟早必须接受的。

Hardware description languages (HDL) have remained at a low semantic level, and have limited abstraction capabilities. These characteristics make the development of VLSI ASICs and FPGAs inherently more difficult and expensive. Research in programming languages and their semantics has established a path toward specification/implementation languages which have much cleaner semantics and strong powers of abstraction. It has been known that such languages could improve the processes of hardware description, synthesis, and verification. But the lack of a method of bridging the large semantic gap between the more powerful languages and Boolean gates has prevented practical progress in this direction. However, work by the applicant and a former PhD student has established an efficient means of synthesizing minimal gate implementations from these abstract languages. This method is based on the computation of frontiers in extended Boolean domains. The proposed work will: a) improve the theoretical basis of the earlier work, b) make the specification language richer and support the new features in the synthesizer, c) embed this specification langauge in Verilog, such that a full Verilog tool chain can be used in experiments, and d) in the longer term, extend this language into the asynchronous design domain which the VLSI community must sooner or later embrace.