Next-Generation of Massively Parallel High-Fidelity Computational Fluid Dynamics

在过去的五年中，大规模并行硬件架构，如NVIDIA的通用图形处理单元和Intel的Xeon Phi加速器，由于其低成本、高能效和高计算吞吐量的结合，在科学和高性能计算社区中获得了牵引力。由于它们的并行架构，更简单的处理器和低时钟频率，这些加速器每teraflops计算消耗更少的功率，并且它们的计算吞吐量比传统cpu以更快的速度增长。庞巴迪宇航公司（BA）的目标是升级他们的全飞机- navier - stokes代码（FANSC），以利用新的硬件架构，而Cray公司的目标是通过对Cray系统的计算流体动力学（CFD）进行彻底的研究来改进他们的专有编译器。本提案的目标是开发新的并行算法，针对FANSC中的算法类型进行定制，并实现它们以充分利用下一代大规模并行硬件架构的计算能力。本研究将通过四个目标来完成：(1)设计和实现异构计算系统的分布式可扩展数据结构；(2)研究大规模并行硬件架构下的CFD求解方法；(3)开发一种新的预处理器，以确保高计算吞吐量和可扩展的流求解器；(4)验证、验证和分析新的FANSC代码。研究目标将通过麦吉尔大学的Siva Nadarajah教授和École Polytechnique的Eric laurenau教授的互补专业知识来实现。所提议的工作的独创性将是对数据结构、求解器和预处理器对可扩展和高效计算框架的同时影响的综合研究。该项目将资助5名研究生和1名博士后。该研究项目将允许麦吉尔大学和École Polytechnique学术团队为大规模并行硬件架构上的CFD算法的进步做出贡献。

For the past five years, massively parallel hardware architectures such as NVIDIA's general purpose graphical processing units and Intel's Xeon Phi accelerators have gained traction in the scientific and high performance computing community due to the combination of their low cost, high power efficiency, and high computational throughput. Thanks to their parallel architecture, simpler processors and low clock frequencies, these accelerators consume less power per teraflops of computations, and their computational throughput is increasing at a greater rate than that of traditional CPUs. Bombardier Aerospace's (BA) objective is to upgrade their Full-Aircraft-Navier-Stokes-Code (FANSC) to take advantage of new hardware architectures, while Cray's objective is to advance their propriety compilers through a thorough investigation of computational fluid dynamics (CFD) on Cray systems. The objective of this proposal is to develop novel parallel algorithms, tailored to the types of algorithms in FANSC and implement them to fully exploit the computational power of the next generation of massively parallel hardware architectures. The research proposed will be accomplished through four objectives: (1) design and implement a distributed scalable data structure for heterogeneous computing systems; (2) research and investigate solvers for CFD on massively parallel hardware architectures; (3) develop a new pre-processor to ensure a high computational throughput and scalable flow solver; (4) validate, verify, and profile the new FANSC code. The research objectives will be met through the combine complimentary expertise of Prof. Siva Nadarajah at McGill University and Prof. Eric Laurendeau at École Polytechnique. The originality of the proposed work will be on the comprehensive research on the simultaneous impact of the data-structure, solver, and pre-processor on a scalable and efficient computational framework. The project will support five graduate students, and a post-doctoral scholar. The research project will allow both the McGill and École Polytechnique academic teams to contribute towards the advancement of algorithms for CFD on massively parallel hardware architectures.