Computer-Aided Design for High-Performance Large-Scale Integrated Circuits

随着电子设备在现代经济中的部署，需要确保电子设备和系统在广泛的部门中的可靠性。集成电路(IC，或简称“芯片”)由于许多故障机制而容易退化和老化，这些故障机制可能会导致芯片在部署后数月或数年出现故障。我们特别关注金属线中的电迁移(EM)，这是一种导致芯片上的金属线在高电流密度下退化和失效的失效机制。随着现代IC技术尺寸的缩小，EM的影响变得更加严重。我的团队开发计算机辅助设计(CAD)工具，以确保芯片在面对EM退化时的健壮性。传统的电磁检测方法基于经验模型，涉及对照特定于技术而不是特定于设计的规范来检查金属线中的电流密度。这些方法易于使用，并为该行业提供了良好的服务，但已不足以满足现代IC技术的要求。在其他方面，这些方法的一个关键缺陷是它们无法跟踪金属原子在金属分支上的移动，导致准确性大大降低。在我们以前的工作中，我们开发了一种基于物理(而不是经验)的电磁检测的有效方法，该方法基于对高电流密度下金属线中发展的机械应力的模拟。这使我们能够在大型多分支金属结构中跟踪金属原子在不同分支上的移动，从而提供显著的精度改进。因此，我们开发了第一个EM应力模拟器[IRPS-19]，该模拟器获得了ICCAD-2016年度最佳论文奖。然而，应力模拟比简单的电流密度检查更耗时，因此需要做更多的工作才能将这些进步转化为行业。该项目旨在解决这一需求，为当前的约束生成提供了一种关键的创新方法。这将涉及到制定和解决压力模拟问题的逆问题，并承诺向研究社区和行业提供高影响力的解决方案。在模拟方法中，模拟器接受给定的输入电流规范，并随时间提供机械应力。相反，鉴于金属网络中任何地方的应力都有安全限制，我们建议对支路电流产生限制，如果设计得到保证，将确保应力在指定的芯片寿命内保持安全。然后，可以在设计期间简单地检查支路电流密度是否满足所产生的电流约束。总体方法将有效地将EM寿命规范转换为技术和设计特定的分支电流约束的规范。它将基于应力的分析的准确性与电流密度检查的速度和简单性结合在一起；这将是两全其美的。

With the deployment of electronics across the modern economy, there is a need to ensure the reliability of electronic devices and systems in a wide range of sectors. Integrated Circuits (ICs, or simply "chips") are subject to degradation and aging due to a number of failure mechanisms that can lead to chip failure, possibly months or years after deployment. We focus specifically on electromigration (EM) in metal lines, a failure mechanism that causes metal lines on a chip to degrade and fail under high current density. The impact of EM has gotten worse with the shrinking dimensions of modern IC technology. My group develops computer-aided design (CAD) tools to ensure chip robustness in the face of EM degradation. Traditional methods of EM checking are based on empirical models and involve checking the current densities in metal lines against specifications that are technology-specific, rather than design-specific. These methods are easy to use and have served the industry well, but have become inadequate for modern IC technology. Among other things, a key failing of these methods is that they cannot track the movement of metal atoms across metal branches, leading to much reduced accuracy. In our previous work, we have developed an efficient approach for physics-based (rather than empirical) EM checking, based on simulation of the mechanical stress that develops in metal lines under high current density. This allows us to track the movement of metal atoms across different branches in large multi-branch metal structures, providing significant accuracy improvement. We have thus developed the first-ever EM stress simulator [IRPS-19], which was recognized with a Best Paper Award in ICCAD-2016. However, stress simulation is more time-consuming than a simple current density check, so more work is required before these advances can be transferred to the industry. This project aims to address this need, with a key innovative approach for current constraints generation. This would involve formulating and solving the inverse of the stress simulation problem, and promises to deliver high-impact solutions to both the research community and the industry. In the simulation approach, a simulator takes in the given input current specifications and provides the mechanical stress over time. Instead, given a safety limit on the stress everywhere in a metal network, we propose to generate constraints on the branch currents which, if guaranteed by design, would ensure that the stress remains safe during the specified chip lifetime. One can then simply check during design if the branch current densities satisfy the generated current constraints. The overall approach would effectively translate the EM lifetime specification into a specification of branch current constraints that are both technology and design specific. It would combine the accuracy of stress-based analysis with the speed and simplicity of a current density check; it would be the best of both worlds.